CY7C63413-PVC Cypress Semiconductor Corp, CY7C63413-PVC Datasheet - Page 23

• Manufacturer Part Number: CY7C63413-PVC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413-PVC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1319

Pending interrupt requests are recognized during the last clock cycle of the current instruction. When servicing an interrupt, the
hardware will first disable all interrupts by clearing the Interrupt Enable bit in the Processor Status and Control Register. Next,
the interrupt latch of the current interrupt is cleared. This is followed by a CALL instruction to the ROM address associated with
the interrupt being serviced (i.e., the Interrupt Vector). The instruction in the interrupt table is typically a JMP instruction to the
address of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an
EI instruction. Interrupts can be nested to a level limited only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are automatically stored onto the Program Stack by the
CALL instruction as part of the interrupt acknowledge process. The user firmware is responsible for insuring that the processor
state is preserved and restored during an interrupt. The PUSH A instruction should be used as the first command in the ISR to
save the accumulator value and the POP A instruction should be used just before the RETI instruction to restore the accumulator
value. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed.
15.1
The Interrupt Vectors supported by the USB Controller are listed in Table 15-1 . Although Reset is not an interrupt, per se, the first
instruction executed after a reset is at PROM address 0x0000h - which corresponds to the first entry in the Interrupt Vector Table.
Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes.
Table 15-1. Interrupt Vector Assignments
15.2
Interrupt latency can be calculated from the following equation:
Interrupt Latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +
For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine will execute a min. of 16 clocks (1+10+5) or a max. of 20 clocks (5+10+5) after the interrupt is issued.
Remember that the interrupt latches are sampled at the rising edge of the last clock cycle in the current instruction.
15.2.1
The USB Bus Reset interrupt is asserted when a USB bus reset condition is detected. A USB bus reset is indicated by a single
ended zero (SE0) on the upstream port for more than 8 microseconds.
Reserved
7
Interrupt Vector Number
Interrupt Vectors
Interrupt Latency
USB Bus Reset Interrupt
not applicable
Reserved
10
11
12
1
2
3
4
5
6
7
8
9
(5 clock cycles for the JMP instruction)
6
Figure 15-2. USB End Point Interrupt Enable Register 0x21h (read/write)
Reserved
5
Reserved
ROM Address
4
0x000Ah
0x000Ch
0x000Eh
0x0000h
0x0002h
0x0004h
0x0006h
0x0008h
0x0010h
0x0012h
0x0014h
0x0016h
0x0018h
23
Reserved
3
Execution after Reset begins here.
USB Bus Reset interrupt
128 s timer interrupt
1.024 ms timer interrupt
USB Address A Endpoint 0 interrupt
USB Address A Endpoint 1 interrupt
USB Address A Endpoint 2 interrupt
Reserved
Reserved
Reserved
DAC interrupt
GPIO interrupt
Reserved
Interrupt
Enable
EPA2
R/W
2
Function
CY7C63411/12/13
CY7C63511/12/13
Interrupt
Enable
EPA1
R/W
1
Interrupt
Enable
EPA0
R/W
0