ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 49

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 45. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
Bit
[7:6]
5
4
3
2
1
0
ANALOG INPUTS
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has two fully differential voltage input channels. The
maximum differential input voltage for the V
input pairs is ±0.4 V.
For the ADE7116/ADE7156/ADE7166/ADE7169, PGA1 = 1 is not
recommended because, at full scale, when both I
180° out of phase, the ADC can be overranged. It is recom-
mended, for these products, that PGA1 = 2, 4, 8, or 16 be used.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the GAIN register (see
Table 38 and Figure 41). Bit 2 to Bit 0 select the gain for the PGA
in the current channel, and Bit 7 to Bit 5 select the gain for the
PGA in the voltage channel. Figure 42 shows how a gain selec-
tion for the current channel is made using the gain register.
Interrupt Enable Bit
Reserved
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Description
Reserved.
When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.
P
/V
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
PA
N
and I
and I
P
PB
/I
are
N
Rev. B | Page 49 of 152
PGA2 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
I
I
V
P
N
IN
Figure 42. PGA in Current Channel
7
0
Figure 41. Analog Gain Register
7
0
6
0
6
0
GAIN REGISTER*
5
0
5
0
GAIN[7:0]
K × V
4
0
4
0
3
0
IN
3
0
2
0
CFSIGN_OPT
RESERVED
2
0
1
0
1
0
GAIN (K)
SELECTION
0
0
PGA1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
0
0
ADDR:
0x1B