ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 126

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
UART SERIAL INTERFACE
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 UART can be configured in one of four modes.
•
•
•
•
Variable baud rates are defined by using an internal timer to
generate any rate between 300 bauds/sec and 115,200 bauds/sec.
The UART serial interface provided in the ADE7166/ADE7169/
ADE7566/ADE7569 is a full-duplex serial interface. It is also
receive buffered by storing the first received byte in a receive
buffer until the reception of the second byte is complete. The
physical interface to the UART is provided via the RxD
UART SFRS
Table 139. Serial Port SFRs
SFR
SCON
SBUF
SBAUDT
SBAUDF
Table 140. Serial Communications Control SFR (SCON, Address 0x98)
Bit
[7:6]
5
4
3
2
1
0
Shift register with baud rate fixed at f
8-bit UART with variable baud rate
9-bit UART with baud rate fixed at f
9-bit UART with variable baud rate
Bit Address
0x9F, 0x9E
0x9D
0x9C
0x9B
0x9A
0x99
0x98
Address
0x98
0x99
0x9E
0x9D
Mnemonic
SM0, SM1
SM2
REN
TB8
RB8
TI
RI
Bit Addressable
Yes
No
No
No
Default
00
0
0
0
0
0
0
CORE
CORE
/64 or f
/12
UART serial mode select bits. These bits select the serial port operating mode.
SM0, SM1
00
01
10
11
Multiprocessor communication enable bit. Enables multiprocessor communication in
Mode 2 and Mode 3 and framing error detection in Mode 1.
Serial port receive enable bit. Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
Serial port transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in
Mode 2 and Mode 3.
Serial port receiver (Bit 9). The ninth data bit received in Mode 2 and Mode 3 is latched
into RB8. For Mode 1, the stop bit is latched into RB8.
Serial port transmit interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or
at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3.
TI must be cleared by user software.
Serial port receive interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or
halfway through the stop bit in Mode 1, Mode 2, and Mode 3.
RI must be cleared by user software.
Description
CORE
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received.
If SM2 is cleared, RI is set as soon as the byte of data is received.
In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.
If SM2 is cleared, RI is set as soon as the byte of data is received.
/32
Serial communications control (see Table 140).
Serial port buffer (see Table 141).
Enhanced serial baud rate control (see Table 142).
UART timer fractional divider (see Table 143).
Description
Rev. B | Page 126 of 152
Result (Selected Operating Mode)
Mode 0, shift register, fixed baud rate (f
Mode 1, 8-bit UART, variable baud rate.
Mode 2, 9-bit UART, fixed baud rate (f
Mode 3, 9-bit UART, variable baud rate.
(P1.0/RxD) and TxD (P1.1/TxD) pins, and the firmware
interface is through the SFRs presented in Table 139.
Both the serial port receive and transmit registers are accessed
through the serial port buffer SFR (SBUF, Address 0x99).
Writing to SBUF loads the transmit register, and reading SBUF
accesses a physically separate receive register.
An enhanced UART mode is offered by using the UART timer
and by providing enhanced frame error, break error, and
overwrite error detection. This mode is enabled by setting the
EXTEN bit in the configuration SFR (CFG, Address 0xAF). See
the UART Additional Features section. The enhanced serial
baud rate control SFR (SBAUDT, Address 0x9E) and UART
timer fractional divider SFR (SBAUDF, Address 0x9D) are used
to configure the UART timer and to indicate the enhanced
UART errors.
CORE
CORE
/32) or (f
/12).
CORE
/16).