CY8CTMG201-32LQXI Cypress Semiconductor Corp, CY8CTMG201-32LQXI Datasheet - Page 285
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CY8CTMG201-32LQXI
Manufacturer Part Number
CY8CTMG201-32LQXI
Description
IC MCU 16K FLASH PSOC 32UQFN
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTMG201-32LQXI
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (16 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Processor Series
CY8CTxx2xx
Core
M8C
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-2971
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21.4.26 SLP_CFG3
This register holds the configuration of the wakeup sequence taps.
It is strongly recommended to not alter this register setting .
In the table above, note that the reserved bit is a grayed table cell and is not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 77
Bit
6
5:4
3:2
1:0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
SLP_CFG3 : 1,EDh
Access : POR
Bit Name
in the Sleep and Watchdog chapter.
DBL_TAPS
T2TAP[1:0]
T1TAP[1:0]
T0TAP[1:0]
Name
Sleep Configuration Register 3
7
DBL_TAPS
RW : 1
6
Description
When this bit is set all the tap values (T0, T1, and T2) are doubled for the wakeup sequence.
These bits control the duration of the T2-T4 sequence (see
tap from the WakeupTimer. Note : The T2 delay is only valid for the wakeup sequence. It is not used
for the buzz sequence.
00
01
10
11
These bits control the duration of the T1-T2 sequence (see
tap from the Wakeup Timer.
00
01
10
11
These bits control the duration of the T0-T1 sequence (see
tap from the Wakeup Timer.
00
01
10
11
1 µs
2 µs
5 µs
10 µs
3 µs
4 µs
5 µs
10 µs
10 µs
14 µs
20 µs
30 µs
5
T2TAP[1:0]
RW : 11
4
3
T1TAP[1:0]
RW : 11
Figure 10-2 on page
Figure 10-2 on page
Figure 10-2 on page
2
1,EDh
Register Definitions on
1
T0TAP[1:0]
RW : 11
75) by selecting a
75) by selecting a
75) by selecting a
SLP_CFG3
1,EDh
0
285
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