CY8CTMG201-32LQXI Cypress Semiconductor Corp, CY8CTMG201-32LQXI Datasheet - Page 122

• Manufacturer Part Number: CY8CTMG201-32LQXI
• Description: IC MCU 16K FLASH PSOC 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-32LQXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2971

15.3
The registers shown here are associated with I
associated register table showing the bit structure for that register. The grayed out bits in the tables are reserved bits and are
not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a complete table of I
registers, refer to the
15.3.1
The I
enhanced features. When all bits are left in the default reset
state of ‘0’, the block operates in compatibility mode. Bits 0
through 3 (except bit 2) are RW.
The Enable bit (bit 0) of the I2C_CFG (0,D6h) register
should be set to 1'b1 for the I
a. Non-address BC interrupts are only posted if the BC bit is cleared in
b. Enabling No BC Int has no affect when HW Addr En is enabled and buff-
c. Enabling No BC Int has no affect only at address byte in this configura-
d. Enabling No BC Int has no affect in compatibility mode.
Bit 3: No BC Int. In compatibility mode, every received or
transmitted byte generates a byte complete interrupt. This is
also true in buffered mode regardless of whether the bus is
stalled or not.
I2C Slave
122
0,C8h
On
On
Off
Off
HW Addr
Address
I2C_SCR. Putting the M8C to sleep without clearing the BC bit in
I2C_SCR will mask I
er mode is disabled, even at address byte. The reason is that the receive/
transmit bit must be set by the CPU. In the case of transmit operation,
the byte to transmit must be loaded to the I2C_DATA register.
tion. The reason is that the CPU must write to the ACK bit in the
I2C_SCR register to ACK/NACK the address byte.
EN
2
C Extended Control Register (I2C_XCFG) configures
On
Off
On
Off
Buffer
Mode
Register Definitions
I2C_XCFG
I2C_XCFG Register
Name
2
On
Off
On
Off
On
Off
On
Off
No BC lnt
C interrupts. This will stall the I
“Summary Table of the System Resource Registers” on page
Bit 7
No interrupt.
Interrupt generated
upon every byte.
Interrupt generated
upon every byte.
Interrupt generated
upon every byte.
Generated only at
address byte.
Interrupt generated
upon every byte.
Interrupt generated
upon every byte.
Interrupt generated
upon every byte.
2
C enhanced features to work.
Byte Complete
Interrupt
Bit 6
c
a
b
a
d
2
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
C bus.
No stalling.
SCL stalls at
each byte.
SCL stalls only
at address byte.
SCL stalls at
every byte.
Clock (SCL)
2
Bit 5
C Slave and are listed in address order. Each register description has an
Stalling
Bit 4
Note When this bit is set to a ‘1’, A BC interrupt is not
enabled for any data byte that is automatically ACK’ed (i.e.,
does not require the bus to stall). A BC interrupt is always
generated on any stall so the CPU takes the appropriate
action. When the bit is set, it is possible to implement packet
transfers without CPU intervention by enabling an interrupt
upon the Stop detect.
Bit 1: Buffer Mode. This bit determines the operation
mode of the enhanced buffer module. The following table
describes the available modes.
Bit 0: HW Addr En. When this bit is set to a ‘1’, hardware
address compare is enabled. Upon a compare, the address
is automatically ACK‘ed, and upon a mismatch, the address
is automatically NACK‘ed and the hardware reverts to an
idle state waiting for the next Start detection. You must con-
figure the compare address in the I2C_ADDR register.
When this bit is a ‘0’, bit 3 of the I2C_SCR register is set and
the bus stalls, and the received address is available in the
I2C_DR register to enable the CPU to do a firmware
address compare. The functionality of this bit is independent
of the data buffering mode.
For additional information, refer to the
on page
0
1
Buffer
Mode
No BC Int
Bit 3
226.
Compatible
EZI2C
Name
Bit 2
106.
There is no buffering in the default compatibility
mode. The
or transmitted byte, including address bytes. The
CPU is required to process the interrupt and write
or read the data and status as required to continue
the operation.
The
face to an external master. A specific protocol must
be followed, in which the master controls the RAM
pointer for both read and write operations. The
I
matically generated. The CPU is responsible for
putting valid data into the RAM for external reads,
and for reading received data.
2
C
I
bus is never stalled. Receive ACKs are auto-
2
C
Buffer Mode HW Addr EN
slave appears as a 32-byte RAM inter-
I
2
Bit 1
C
bus is stalled upon every received
Description
I2C_XCFG register
Bit 0
Access
RW : 0
2
C
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