XC4044XLA-08HQ240I Xilinx Inc, XC4044XLA-08HQ240I Datasheet - Page 53
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XC4044XLA-08HQ240I
Manufacturer Part Number
XC4044XLA-08HQ240I
Description
IC FPGA I 2.5V 320 I/O 240HQFP
Manufacturer
Xilinx Inc
Series
XC4000XLA/XVr
Datasheet
1.XC4044XLA-08HQ240I.pdf
(68 pages)
Specifications of XC4044XLA-08HQ240I
Number Of Logic Elements/cells
3800
Number Of Labs/clbs
1600
Total Ram Bits
51200
Number Of I /o
193
Number Of Gates
44000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
155001B
Q1155001B
XC4044XLA08HQ240I
Q1155001B
XC4044XLA08HQ240I
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4044XLA-08HQ240I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4044XLA-08HQ240I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC4000E/EX/XL Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Note 1:
Note 2:
Note 1:
Note 2:
May 14, 1999 (Version 1.6)
E/EX
rdbk.TRIG
rdclk.1
XL
rdbk.TRIG
rdclk.1
Internal Net
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
rdbk.DATA
rdbk.TRIG
rdbk.RIP
Finished
rdclk.I
R
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
4
1
T
T
RCL
RTRC
T
RCRT
DUMMY
XC4000E and XC4000X Series Field Programmable Gate Arrays
T
T
RCRD
T
RCRR
RCH
2
7
5
6
DUMMY
1
T
RTRC
VALID
T
RCRT
VALID
1
2
7
6
5
4
1
2
7
6
5
4
2
Symbol
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
RCRD
RCRR
RCRD
RCRR
RTRC
RCRT
RTRC
RCRT
RCH
RCH
RCL
RCL
Min
200
250
250
Min
200
250
250
50
50
-
-
-
-
Max
Max
250
250
500
500
250
250
500
500
-
-
-
-
X1790
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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