XC5204-6PQ160C Xilinx Inc, XC5204-6PQ160C Datasheet - Page 26
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XC5204-6PQ160C
Manufacturer Part Number
XC5204-6PQ160C
Description
IC FPGA 120 CLB'S 160-PQFP
Manufacturer
Xilinx Inc
Series
XC5200r
Datasheet
1.XC5206-5PQ208C.pdf
(73 pages)
Specifications of XC5204-6PQ160C
Number Of Logic Elements/cells
480
Number Of Labs/clbs
120
Number Of I /o
124
Number Of Gates
6000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-BQFP
Case
QFP160
Dc
00+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
122-1135
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5204-6PQ160C
Manufacturer:
XILINX
Quantity:
513
Part Number:
XC5204-6PQ160C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC5200 Series Field Programmable Gate Arrays
Configuration Sequence
There are four major steps in the XC5200-Series power-up
configuration sequence.
• Power-On Time-Out
• Initialization
• Configuration
• Start-Up
The full process is illustrated in
Power-On Time-Out
An internal power-on reset circuit is triggered when power
is applied. When V
of the FPGA begin to operate (i.e., performs a
write-and-read test of a sample pair of configuration mem-
ory bits), the programmable I/O buffers are 3-stated with
active high-impedance pull-up resistors. A time-out delay
— nominally 4 ms — is initiated to allow the power-supply
voltage to stabilize. For correct operation the power supply
must reach V
not dip below it thereafter.
There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have com-
pleted initialization. Since XC2000 devices do not have this
signal, extra care must be taken to guarantee proper oper-
ation when daisy-chaining them with XC5200 devices. For
proper operation with XC3000 devices, the RESET signal,
which is used in XC3000 to delay configuration, should be
connected to INIT.
If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM
pin Low. During all three phases — Power-on, Initialization,
and Configuration — DONE is held Low; HDC, LDC, and
INIT are active; DOUT is driven; and all I/O buffers are dis-
abled.
7-108
Figure 23: Circuit for Generating CRC-16
0
1
LAST DATA FRAME
1
X2
1
CC
1
2 3 4 5 6 7 8 9 10 11 12 13 14
1
(min) by the end of the time-out, and must
1 0 15 14 13 12 11 10 9 8 7 6 5
CC
Polynomial: X16 + X15 + X2 + 1
reaches the voltage at which portions
Readback Data Stream
Product Obsolete or Under Obsolescence
CRC – CHECKSUM
Figure
SERIAL DATA IN
24.
X15
X1789
15
X16
Initialization
This phase clears the configuration memory and estab-
lishes the configuration mode.
The configuration memory is cleared at the rate of one
frame per internal clock cycle (nominally 1 MHz). An
open-drain bidirectional signal, INIT, is released when the
configuration memory is completely cleared. The device
then tests for the absence of an external active-low level on
INIT. The mode lines are sampled two internal clock cycles
later (nominally 2 s).
The master device waits an additional 32
(nominally 64-128 s) to provide adequate time for all of the
slave devices to recognize the release of INIT as well. Then
the master device enters the Configuration phase.
Figure 24: Configuration Sequence
(*only when PROGRAM = High)
SAMPLE PRELOAD
SAMPLE/PRELOAD*
SAMPLE/PRELOAD
Boundary Scan
CONFIGURE*
Instructions
CONFIGURE
Available:
EXTEST*
BYPASS
BYPASS
READBACK
BYPASS
EXTEST
USER 1
USER 2
Goes Active after
Master CCLK
50 to 250 s
If Boundary Scan
is Selected
F
One Time-Out Pulse
Completely Clear
November 5, 1998 (Version 5.2)
Data to DOUT
Count Equals
Configuration
Configuration
Configuration
Operational
Data Frame
Mode Lines
Sequence
Generate
Yes
Load One
Yes
Yes
Yes
No
Memory
Start-Up
High? if
Sample
memory
of 4 ms
Config-
Length
Master
Frame
uration
CCLK
Count
V CC
Error
Pass
INIT
Full
3V
Yes
No
No
No
No
~1.3 s per Frame
Pull INIT Low
and Stop
PROGRAM
= Low
Yes
s to 256
X9017
R
s