XC5202-6PC84C Xilinx Inc, XC5202-6PC84C Datasheet - Page 30

• Manufacturer Part Number: XC5202-6PC84C
• Description: IC FPGA 64 CLB'S 84-PLCC
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5202-6PC84C

• Number Of Logic Elements/cells: 256
• Number Of Labs/clbs: 64
• Number Of I /o: 65
• Number Of Gates: 3000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 9629
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1131

XC5200 Series Field Programmable Gate Arrays
DONE High to active user I/O is controlled by an option to
the bitstream generation software.
Release of Global Reset After DONE Goes High
By default, Global Reset (GR) is released two CCLK cycles
after the DONE pin goes High. If CCLK is not clocked twice
after DONE goes High, all flip-flops are held in their initial
reset state. The delay from DONE High to GR inactive is
controlled by an option to the bitstream generation soft-
ware.
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
7-112
Figure 26: Start-up Logic
CLEAR MEMORY
LENGTH COUNT
STARTUP
STARTUP.CLK
USER NET
CCLK
FULL
Q3
Q2
*
*
*
S
K
Product Obsolete or Under Obsolescence
Q
Figure 25 on page
Q0
0
1
M
*
1
0
*
1
0
0
1
Q1/Q4
DONE
IN
D
K
GR ENABLE
GR INVERT
STARTUP.GR
STARTUP.GTS
GTS INVERT
GTS ENABLE
CONFIGURATION BIT OPTIONS SELECTED BY USER
Q
109. If CCLK is
Q1
D
K
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
Q
Q2
1
0
M
*
Configuration Through the Boundary Scan
Pins
XC5200-Series devices can be configured through the
boundary scan pins.
For detailed information, refer to the Xilinx application note
XAPP017, “ Boundary Scan in XC4000 and XC5200
Devices .”
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs.
D
Q
K
S
R
Q
Q3
GLOBAL RESET OF
ALL CLB FLIP-FLOPS/LATCHES
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL 3-STATE OF ALL IOBs
D
K
Q
Q4
November 5, 1998 (Version 5.2)
1
0
X9002
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
DONE
R