XC5202-6PC84C Xilinx Inc, XC5202-6PC84C Datasheet - Page 11

• Manufacturer Part Number: XC5202-6PC84C
• Description: IC FPGA 64 CLB'S 84-PLCC
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5202-6PC84C

• Number Of Logic Elements/cells: 256
• Number Of Labs/clbs: 64
• Number Of I /o: 65
• Number Of Gates: 3000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 9629
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1131

to Vcc. The configurable pull-down resistor is an n-channel
transistor that pulls to Ground.
The value of these resistors is 20 k
value makes them unsuitable as wired-AND pull-up resis-
tors.
The pull-up resistors for most user-programmable IOBs are
active during the configuration process. See
page 124
during configuration.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis-
tor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal
pull-up, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
JTAG Support
Embedded logic attached to the IOBs contains test struc-
tures compatible with IEEE Standard 1149.1 for boundary
scan testing, simplifying board-level testing. More informa-
tion is provided in
Oscillator
XC5200 devices include an internal oscillator. This oscilla-
tor is used to clock the power-on time-out, clear configura-
tion memory, and source CCLK in Master configuration
modes. The oscillator runs at a nominal 12 MHz frequency
that varies with process, Vcc, and temperature. The output
CCLK frequency is selectable as 1 MHz (default), 6 MHz,
or 12 MHz.
The XC5200 oscillator divides the internal 12-MHz clock or
a user clock. The user then has the choice of dividing by 4,
16, 64, or 256 for the “OSC1” output and dividing by 2, 8,
32, 128, 1024, 4096, 16384, or 65536 for the “OSC2” out-
put. The division is specified via a “DIVIDEn_BY=x”
attribute on the symbol, where n=1 for OSC1, or n=2 for
OSC2. These frequencies can vary by as much as -50% or
+ 50%.
The OSC5 macro is used where an internal oscillator is
required. The CK_DIV macro is applicable when a user
clock input is specified (see
November 5, 1998 (Version 5.2)
for a list of pins with pull-ups active before and
R
“Boundary Scan” on page
Product Obsolete or Under Obsolescence
Figure
13).
100 k . This high
98.
Table 13 on
XC5200 Series Field Programmable Gate Arrays
VersaBlock Routing
The General Routing Matrix (GRM) connects to the
Versa-Block via 24 bidirectional ports (M0-M23). Excluding
direct connections, global nets, and 3-statable Longlines,
all VersaBlock inputs and outputs connect to the GRM via
these 24 ports. Four 3-statable unidirectional signals
(TQ0-TQ3) drive out of the VersaBlock directly onto the
horizontal and vertical Longlines. Two horizontal global
nets and two vertical global nets connect directly to every
CLB clock pin; they can connect to other CLB inputs via the
GRM. Each CLB also has four unidirectional direct con-
nects to each of its four neighboring CLBs. These direct
connects can also feed directly back to the CLB (see
Figure
In addition, each CLB has 16 direct inputs, four direct con-
nections from each of the neighboring CLBs. These direct
connections
bypasses the GRM.
Local Interconnect Matrix
The Local Interconnect Matrix (LIM) is built from input and
output multiplexers. The 13 CLB outputs (12 LC outputs
plus a V
outputs via the output multiplexers, which consist of eight
fully
CLB directly, and provide a direct feedback path to the input
multiplexers. The four remaining multiplexer outputs can
drive the GRM through four TBUFs (TQ0-TQ3). All eight
multiplexer outputs can connect to the GRM through the
bidirectional M0-M23 signals. All eight signals also connect
to the input multiplexers and are potential inputs to that
CLB.
Figure 13: XC5200 Oscillator Macros
VersaBlock outputs, four signals drive each neighboring
populated
14).
cc
/GND signal) connect to the eight VersaBlock
provide
13-to-1
CK_DIV
OSCS
high-speed
multiplexers.
OSC1
OSC2
OSC1
OSC2
5200_14
local
Of
routing
the
eight
7-93
that
7