XC4010-5PQ208C Xilinx Inc, XC4010-5PQ208C Datasheet - Page 34

• Manufacturer Part Number: XC4010-5PQ208C
• Description: IC LOGIC CL ARRAY 10K GAT 208PQ
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Case: QFP208
• Dc: 96+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1071

XC4000, XC4000A, XC4000H Logic Cell Array Families
Asynchronous Peripheral Mode
Write to LCA
Asynchronous Peripheral mode uses the trailing edge of
the logic AND condition of the CS0, CS1 and WS inputs to
accept byte-wide data from a microprocessor bus. In the
lead LCA device, this data is loaded into a double-buffered
UART-like parallel-to-serial converter and is serially shifted
into the internal logic. The lead LCA device presents the
preamble data (and all data that overflows the lead device)
on the DOUT pin.
The RDY/BUSY output from the lead LCA device acts as
a handshake signal to the microprocessor. RDY/BUSY
goes Low when a byte has been received, and goes High
again when the byte-wide input buffer has transferred its
information into the shift register, and the buffer is ready to
receive new data. The length of the BUSY signal depends
on the activity in the UART. If the shift register had been
empty when the new byte was received, the BUSY signal
lasts for only two CCLK periods. If the shift register was still
full when the new byte was received, the BUSY signal can
be as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
The READY/BUSY handshake can be ignored if the delay
from any one Write to the end of the next Write is guaran-
teed to be longer than 10 CCLK periods,i.e. longer than 20
s.
CONTROL
SIGNALS
+5 V
ADDRESS
REPROGRAM
DATA
BUS
BUS
ADDRESS
DECODE
LOGIC
8
2-40
Status Read
The logic AND condition of the CS0, CS1and RS inputs
puts the device status on the Data bus.
It is mandatory that the whole start-up sequence be started
and completed by one byte-wide input. Otherwise, the pins
used as Write Strobe or Chip Enable might become active
outputs and inteffere with the final byte transfer. If this
transfer does not occur, the start-up sequence will not be
completed all the way to the finish (point F in Figure 21 on
page 2-29). At worst, the internal reset will not be released;
at best, Readback and Boundary Scan will be inhibited.
The length-count value, as generated by MAKEPROM, is
supposed to ensure that these problems never occur.
Although RDY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
one of the data lines. For this purpose, D7 represents the
RDY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.
How to Delay Configuration After Power-Up
There are two methods to delay configuration after power-
up: Put a logic Low on the PROGRAM input, or pull the
bidirectional INIT pin Low, using an open-collector (open-
drain) driver. (See also Figure 20 on page 2-27).
D7 = High indicates Ready
D7 - Low indicates Busy
D0 through D6 go unconditionally High
CS0
DONE
D0–7
CS1
RS
WS
RDY/BUSY
INIT
PROGRAM
M0
XC4000
I/O PINS
M1
OTHER
DOUT
M2
CCLK
HDC
LDC
GENERAL-
PURPOSE
USER I/O
PINS
OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH
DIFFERENT
CONFIGURATIONS
+5 V
X3396