XC4010-5PQ208C Xilinx Inc, XC4010-5PQ208C Datasheet - Page 30

• Manufacturer Part Number: XC4010-5PQ208C
• Description: IC LOGIC CL ARRAY 10K GAT 208PQ
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Case: QFP208
• Dc: 96+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1071

XC4000, XC4000A, XC4000H Logic Cell Array Families
Master Parallel Mode
In Master Parallel mode, the lead LCA device directly ad-
dresses an industry-standard byte-wide EPROM, and ac-
cepts eight data bits right before incrementing (or
decrementing) the address outputs.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data ( and all data that
overflows the lead device ) on the DOUT pin. There is an
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data (and also changes the
EPROM address) until the falling CCLK edge that makes
the LSB (D0) of this byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy-chain accepts data on the subse-
quent rising CCLK edge.
PROGRAM
GENERAL-
PURPOSE
USER I/O
PINS
DOUT
HDC
RCLK
RCLK
PROGRAM
D7
D6
D5
D4
D3
D2
D1
D0
LDC
INIT
M0
OTHER
I/O PINS
HIGH
LOW
XC4000
M1
or
DATA BUS
+5 V
M2
DONE
CCLK
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
. . .
. . .
. . .
. . .
. . .
2-36
TO DIN OF OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH
DIFFERENT CONFIGURATIONS
OE
CE
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(OR LARGER)
EPROM
(8K x 8)
How to Delay Configuration After Power-Up
There are two methods to delay configuration after power-
up: Put a logic Low on the PROGRAM input, or pull the
bidirectional INIT pin Low, using an open-collector (open-
drain) driver. (See also Figure 20 on page 2-27).
A Low on the PROGRAM input is the more radical ap-
proach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the XC4000 device keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output.
D7
D6
D5
D4
D3
D2
D1
D0
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS
X3394