XC5VLX220-2FF1760I Xilinx Inc, XC5VLX220-2FF1760I Datasheet - Page 131

• Manufacturer Part Number: XC5VLX220-2FF1760I
• Description: IC FPGA VIRTEX-5 220K 1760FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-2FF1760I

• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Block RAM Initialization in VHDL or Verilog Code
Additional RAMB18 and RAMB36 Primitive Design Considerations
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Block RAM Location Constraints
Optional Output Registers
Independent Read and Write Port Width
Block RAM instances can have LOC properties attached to them to constrain placement.
Block RAM placement locations differ from the convention used for naming CLB locations,
allowing LOC properties to transfer easily from array to array.
The LOC properties use the following form:
The RAMB36_X0Y0 is the bottom-left block RAM location on the device. If RAMB36 is
constrained to RAMB36_X#Y#, the FIFO cannot be constrained to FIFO36_X#Y# since they
share a location.
Two RAMB18s can be placed in the same RAMB36 location by using the BEL
UPPER/LOWER constraint:
In addition, one FIFO18 and one RAMB16 can be placed in the same RAMB36 location, no
BEL constraint is required:
Block RAM memory attributes and content can be initialized in VHDL or Verilog code for
both synthesis and simulation by using generic maps (VHDL) or defparams (Verilog)
within the instantiated component. Modifying the values of the generic map or defparam
will effect both the simulation behavior and the implemented synthesis results. The
Virtex-5 FPGA Libraries Guide includes the code to instantiate the RAMB36 primitive.
The RAMB18 and RAMB36 primitives are integral in the Virtex-5 FPGA block RAM
solution.
Optional output registers can be used at either or both A|B output ports of RAMB18 and
RAMB36. The choice is made using the DO[A|B]_REG attribute. The two independent
clock enable pins are REGCE[A|B]. When using the optional output registers at port
[A|B], assertion of the synchronous set/reset (SSR) pin of ports [A|B] causes the value
specified by the attribute SRVAL to be registered at the output.
optional output register.
To specify the port widths using the dual-port mode of the block RAM, designers must use
the READ_WIDTH_[A|B] and WRITE_WIDTH_[A|B] attributes. The following rules
should be considered:
•
•
LOC = RAMB36_X#Y#
inst ”my_ramb18” LOC = RAMB36_X0Y0 | BEL = UPPER
inst ”my_ramb18” LOC = RAMB36_X0Y0 | BEL = LOWER
inst ”my_fifo18” LOC = RAMB36_X0Y0
inst ”my_ramb18” LOC = RAMB36_X0Y0
Designing a single port block RAM requires the port pair widths of one write and one
read to be set (e.g., READ_WIDTH_A and WRITE_WIDTH_A).
Designing a dual-port block RAM requires all port widths to be set.
www.xilinx.com
Block RAM Initialization in VHDL or Verilog Code
Figure 4-5
shows an
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