XCV812E-7BG560C Xilinx Inc, XCV812E-7BG560C Datasheet - Page 74

• Manufacturer Part Number: XCV812E-7BG560C
• Description: IC FPGA 1.8V C-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-7BG560C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 404
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those
parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the
recommended operating conditions.
Module 3 of 4
18
Input Clock Frequency (CLKDLLHF)
Input Clock Frequency (CLKDLL)
Input Clock Low/High Pulse Width
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
Period Tolerance: the allowed input clock period change in nanoseconds.
Actual Period
Ideal Period
Description
T CLKIN
FCLKINHF
FCLKINLF
Symbol
T
Figure 4: DLL Timing Waveforms
DLLPW
www.xilinx.com
1-800-255-7778
≥100 MHz
≥150 MHz
≥200 MHz
≥250 MHz
≥300 MHz
≥25 MHz
≥50 MHz
F
CLKIN
Phase Offset and Maximum Phase Difference
Min
5.0
3.0
2.4
2.0
1.8
1.5
1.3
60
25
+/- Jitter
+ Maximum
+ Phase Offset
-8
Phase Difference
Max
320
160
Speed Grade
T CLKIN + T IPTOL
Min
5.0
3.0
2.4
2.0
1.8
1.5
1.3
60
25
-7
ds022_24_091200
_
Max
320
160
DS025-3 (v2.3.2) March 14, 2003
Min
5.0
3.0
2.4
2.0
1.8
1.5
NA
60
25
-6
Max
260
135
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
R