XC4VFX60-11FFG1152I Xilinx Inc, XC4VFX60-11FFG1152I Datasheet - Page 207
XC4VFX60-11FFG1152I
Manufacturer Part Number
XC4VFX60-11FFG1152I
Description
IC FPGA VIRTEX-4 FX 60K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX60-11FFG1152I
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Total Ram Bits
4276224
Number Of I /o
576
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-BBGA, FCBGA
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Timing Characteristics
Figure 5-21
•
•
•
At time T
the CE input of the slice register.
At time T
FXINB inputs become valid-High at the D input of the slice register and is reflected on
either the XQ or YQ pin at time T
At time T
this case) becomes valid-High, resetting the slice register. This is reflected on the XQ
or YQ pin at time T
illustrates the general timing characteristics of a Virtex-4 FPGA slice.
SRCK
CECK
DICK
(RESET)
DI/FX
(DATA)
Figure 5-21: General Slice Timing Characteristics
(OUT)
CLK
or T
before clock event (3), the SR signal (configured as synchronous reset in
before clock event (1), the clock-enable signal becomes valid-High at
YQ
CE
SR
FXCK
CKO
www.xilinx.com
after clock event (3).
before clock event (1), data from either BX, BY, FXINA or
1
T
T
CECK
DICK
T
CKO
CKO
/
T
FXCK
after clock event (1).
2
3
T
SRCK
CLB / Slice Timing Models
UG070_5_21_080204
T
CKO
207
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