XCV812E-6BG560C Xilinx Inc, XCV812E-6BG560C Datasheet - Page 29

• Manufacturer Part Number: XCV812E-6BG560C
• Description: IC FPGA 1.8V C-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-6BG560C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 404
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 560-LBGA, Metal
• Dc: 0325
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Operating Modes
Virtex-E block SelectRAM+ memory supports two operating
modes.
•
•
Read Through (one clock edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the out-
puts, depending on the desire to have a faster clock-to-out
versus set-up time. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the read
pulse clock.
Write Back (one clock edge)
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.
Block SelectRAM+ Characteristics
1. All inputs are registered with the port clock and have a
2. All outputs have a read through or write back function
3. The block SelectRAM elements are true SRAM
4. The ports are completely independent from each other
5. A write operation requires only one clock edge.
6. A read operation requires only one clock edge.
The output ports are latched with a self-timed circuit to guar-
antee a glitch-free read. The state of the output port does
not change until the port executes another read or write
operation.
Library Primitives
Figure 31
SelectRAM+ primitives.
able primitives for synthesis and simulation.
DS025-2 (v2.3) November 19, 2002
Read Through
Write Back
set-up to clock timing specification.
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
memories and do not have a combinatorial path from
the address to the output. The LUT SelectRAM+ cells in
the CLBs are still available with this function.
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
and
R
Figure 32
Table 14
show the two generic library block
describes all of the avail-
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
Table 14:
RAMB4_S1
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
RAMB4_S2
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
RAMB4_S4
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
RAMB4_S8
RAMB4_S8_S8
RAMB4_S8_S16
RAMB4_S16
RAMB4_S16_S16
Figure 32: Single-Port Block SelectRAM+ Memory
Figure 31: Dual-Port Block SelectRAM+ Memory
Primitive
Available Library Primitives
WEA
ENA
RSTA
ADDRA[#:0]
DIA[#:0]
WEB
ENB
RSTB
ADDRB[#:0]
DIB[#:0]
CLKA
CLKB
WE
EN
RST
ADDR[#:0]
DI[#:0]
CLK
RAMB4_S#_S#
RAMB4_S#
Port A Width
16
1
2
4
8
ds022_033_121399
DO[#:0]
DOA[#:0]
DOB[#:0]
ds022_032_121399
Port B Width
Module 2 of 4
N/A
N/A
N/A
N/A
N/A
16
16
16
16
16
1
2
4
8
2
4
8
4
8
8
25