XC5VSX50T-1FFG1136C Xilinx Inc, XC5VSX50T-1FFG1136C Datasheet - Page 317

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VSX50T-1FFG1136C

Manufacturer Part Number
XC5VSX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG1136C

Total Ram Bits
4866048
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
4080
No. Of Macrocells
50000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1567

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VSX50T-1FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX50T-1FFG1136C
Manufacturer:
XILINX
0
Part Number:
XC5VSX50T-1FFG1136C
0
SelectIO Logic Resources
Introduction
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
This chapter describes the logic directly behind the I/O drivers and receivers covered in
Chapter 6, SelectIO
Virtex-5 FPGAs contain all of the basic I/O logic resources from Virtex-II/Virtex-II Pro
FPGAs. These resources include the following:
In addition, Virtex-5 FPGAs implement the following architectural features that are also
supported in Virtex-4 FPGAs:
Combinatorial input/output
3-state output control
Registered input/output
Registered 3-state output control
Double-Data-Rate (DDR) input/output
DDR output 3-state control
IODELAY provides users control of an adjustable, fine-resolution delay element
SAME_EDGE output DDR mode
SAME_EDGE and SAME_EDGE_PIPELINED input DDR mode
Resources.
www.xilinx.com
Chapter 7
317

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