XC4VFX40-11FFG1152C Xilinx Inc, XC4VFX40-11FFG1152C Datasheet - Page 371
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XC4VFX40-11FFG1152C
Manufacturer Part Number
XC4VFX40-11FFG1152C
Description
IC FPGA VIRTEX-4 FX 40K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX40-11FFG1152C
Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC4VFX40-11FFG1152C
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Xilinx Inc
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10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Clock Event 2
The reset pulse is deasserted on the rising edge of CLKDIV. The difference in propagation
delay between the two ISERDES causes the SR input to come out of reset in two different
CLK cycles. If there were no internal re-timing, ISERDES1 would come out of reset one
CLK cycle before ISERDES0, which would leave both ISERDES out of sync.
Clock Event 3
The release of the reset signal at the SR input is re-timed internally to CLKDIV. This brings
ISERDES 0 and 1 back into sync.
Clock Event 4
The release of the reset signal at the SR input is re-timed internally to CLK.
Figure 8-5: Two ISERDES Coming Out of Reset Synchronously with One Another
Internal Reset
Internal Reset
(CLKDIV)
Signal at
SR Input
(CLK)
www.xilinx.com
ISERDES0
ISERDES1
ISERDES0
ISERDES1
ISERDES0
ISERDES1
CLKDIV
CLK
Input Serial-to-Parallel Logic Resources (ISERDES)
Event 1
Clock
Event 2
Clock
Event 3
Clock
Clock
Event 4
UG070_c8_21_041007
371
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