XC4VFX40-11FFG1152C Xilinx Inc, XC4VFX40-11FFG1152C Datasheet - Page 347
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XC4VFX40-11FFG1152C
Manufacturer Part Number
XC4VFX40-11FFG1152C
Description
IC FPGA VIRTEX-4 FX 40K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX40-11FFG1152C
Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Company:
Part Number:
XC4VFX40-11FFG1152C
Manufacturer:
Xilinx Inc
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10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Verilog Use Model
-- The user either declares the LOC constraints in the
-- VHDL design file, or in the UCF file.
-- Declaring LOC constraints in the VHDL file.
attribute loc : string;
attribute loc of dlyctrl_1:label is "IDELAYCTRL_X0Y0";
attribute loc of dlyctrl_2:label is "IDELAYCTRL_X0Y1";
.
.
.
attribute loc of dlyctrl_n:label is "IDELAYCTRL_XnYn";
-- Declaring LOC constraints in the UCF file.
INST "dlyctrl_1" LOC=IDELAYCTRL_X0Y0;
INST "dlyctrl_2" LOC=IDELAYCTRL_X0Y1;
.
.
.
INST "dlyctrl_n" LOC=IDELAYCTRL_XnYn;
// Multiple instances of IDELAYCTRL primitives are instantiated.
// Each instance has its own RST and RDY signal to allow for partial
// reconfiguration.
// The REFCLK signal is common to all instances
IDELAYCTRL dlyctrl_1 (
IDELAYCTRL dlyctrl_2 (
.
.
.
IDELAYCTRL dlyctrl_n (
// The user either declares the LOC constraints in the
// Verilog design file or in the following UCF file.
// Declaring LOC constraints in the Verilog file.
// synthesis attribute loc of dlyctrl_1 is "IDELAYCTRL_X0Y0";
// synthesis attribute loc of dlyctrl_2 is "IDELAYCTRL_X0Y1";
.
.
.
// synthesis attribute loc of dlyctrl_N is "IDELAYCTRL_XnYn";
// Declaring LOC constraints in the UCF file:
INST "dlyctrl_1" LOC=IDELAYCTRL_X0Y0;
www.xilinx.com
);
RST => rst_n
);
);
);
.RDY(rdy _1),
.REFCLK(refclk),
.RST(rst_1)
.RDY(rdy_2),
.REFCLK(refclk),
.RST(rst_2)
.RDY(rdy_n),
.REFCLK(refclk),
.RST(rst_n)
ILOGIC Resources
347
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