XC5VLX30-2FF676I Xilinx Inc, XC5VLX30-2FF676I Datasheet - Page 49
![IC FPGA VIRTEX-5 30K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-2FF676I
Manufacturer Part Number
XC5VLX30-2FF676I
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-2FF676I
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
•
•
•
Frequency Synthesis
Separate outputs provide a doubled frequency (CLK2X and CLK2X180). Another
output, CLKDV, provides a frequency that is a specified fraction of the input
frequency.
Two other outputs, CLKFX and CLKFX180, provide an output frequency derived from
the input clock by simultaneous frequency division and multiplication. The user can
specify any integer multiplier (M) and divisor (D) within the range specified in the
DCM Timing Parameters section of the Virtex-5 FPGA Data Sheet. An internal
calculator determines the appropriate tap selection, to make the output edge coincide
with the input clock whenever mathematically possible. For example, M = 9 and D = 5,
multiply the frequency by 1.8, and the output rising edge is coincident with the input
rising edge after every fifth input period, or after every ninth output period.
Phase Shifting
The DCM allows coarse and fine-grained phase shifting. The coarse phase shifting
uses the 90°, 180°, and 270° phases of CLK0 to make CLK90, CLK180, and CLK270
clock outputs. The 180° phase of CLK2X and CLKFX provide the respective CLK2X180
and CLKFX180 clock outputs.
There are also four modes of fine-grained phase-shifting; fixed, variable-positive,
variable-center, and direct modes. Fine-grained phase shifting allows all DCM output
clocks to be phase-shifted with respect to CLKIN while maintaining the relationship
between the coarse phase outputs. With fixed mode, a fixed fraction of phase shift can
be defined during configuration and in multiples of the clock period divided by 256.
Using the variable-positive and variable-center modes the phase can be dynamically
and repetitively moved forward and backwards by 1/256 of the clock period. With the
direct mode the phase can be dynamically and repetitively moved forward and
backwards by the value of one DCM_TAP. See the DCM Timing Parameters section in
the Virtex-5 FPGA Data Sheet.
Dynamic Reconfiguration
There is a bus connection to the DCM to change DCM attributes without reconfiguring
the rest of the device. For more information, see the Dynamic Reconfiguration chapter
of the Virtex-5 FPGA Configuration Guide.
The DADDR[6:0], DI[15:0], DWE, DEN, DCLK inputs and DO[15:0], and DRDY
outputs are available to dynamically reconfigure select DCM functions. With dynamic
reconfiguration, DCM attributes can be changed to select a multiply (M) or divide (D)
from the currently configured settings.
www.xilinx.com
DCM Summary
49
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