XC5VLX30-2FF676I Xilinx Inc, XC5VLX30-2FF676I Datasheet - Page 33
![IC FPGA VIRTEX-5 30K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-2FF676I
Manufacturer Part Number
XC5VLX30-2FF676I
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-2FF676I
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Figure 1-7
X-Ref Target - Figure 1-7
BUFGMUX and BUFGMUX_1
BUFGMUX is a clock buffer with two clock inputs, one clock output, and a select line. This
primitive is based on BUFGCTRL with some pins connected to logic High or Low.
Figure 1-8
available for BUFGMUX and BUFGCTRL.
X-Ref Target - Figure 1-8
Since the BUFGMUX uses the CE pins as select pins, when using the select, the setup time
requirement must be met. Violating this setup time might result in a glitch.
Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL.
Figure 1-9
BUFGCE_1(CE)
BUFGCE_1(O)
illustrates the timing diagram for BUFGCE_1.
illustrates the relationship of BUFGMUX and BUFGCTRL. A LOC constraint is
illustrates the timing diagram for BUFGMUX.
BUFGCE_1(I)
I1
I0
S
BUFGMUX
Figure 1-7: BUFGCE_1 Timing Diagram
Figure 1-8: BUFGMUX as BUFGCTRL
www.xilinx.com
O
T
BCCKO_O
S
GND
GND
V
V
T
DD
DD
BCCCK_CE
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Global Clocking Resources
ug190_1_08_032206
ug190_1_07_032206
O
33
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