XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 88
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XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
DS202 (v5.3) May 5, 2010
Product Specification
05/18/07
06/15/07
Date
Version
3.1
3.2
• Added typical values for n and r in
• Revised and added values to
• Revised standard I/O levels in
• Additions and updates to
• Added
• Changed the design software version that matches this data sheet above
• Added new section:
• In
• Revised -1 speed F
• Added Note 4 to T
• Added ± values to
• In
• In
• In
• Updated T
• Corrected V
• Changed the design software version that matches this data sheet above
• Added
• Added T
• In
• In
• Corrected units to ns in
and
• LVTTL, Slow and Fast, 2 mA, 4 mA, and 6 mA
• LVCMOS33, Slow and Fast, 2 mA, 4 mA, and 6 mA
• LVCMOS25, Slow and Fast, 2 mA and 4 mA, and Fast 12 mA
• LVCMOS18, Slow and Fast, 2 mA, 4 mA, and 6 mA
• LVCMOS15 and LVCMOS12, Slow and Fast, 2 mA
• T
• Setup/Hold for Control Lines and Data Lines in
• Add T
• Revised T
• Replaced T
• Revised T
• Revised T
• Revised Hold Times of Data/Control Pins to the Input Register Clock.
• Updated and added values to
• Revised values in
• Revised values in
• Revised values in
• Added package skew values to
• Revised values in
Table
Switching
Virtex-5 Device Pin-to-Pin Output Parameter
Virtex-5 Device Pin-to-Pin Input Parameter
Source-Synchronous Switching
Virtex-5 Device Pin-to-Pin Output Parameter
Virtex-5 Device Pin-to-Pin Input Parameter
Setup/Hold times of {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK. Hold times of
some of the CE pins. Hold times of some of the RST pins. Hold times of {A, B} input to {P,
CARRYOUT} output using multiplier and {ACIN, BCIN} input to {P, CARRYOUT} output using
multiplier, CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier, in
Table
IDOCK
90.
Ethernet MAC Switching Characteristics, page
Production Silicon and ISE Software Status, page
IODELAY_CLK_MAX
IDELAYPAT_JIT
35.
STG
and T
OH
Characteristics, the following values are revised:
RCK
CECK
RCKO_FLAGS
TWC
/V
in
IDOCKD
OL
Table
page 45
LOCKMAX
in
Table 79
with T
MAX
in
I/O Standard Adjustment Measurement Methodology, page
Table
Table 84
Table 91
Table 98, page
Table 101, page
Table 9
and revised T
1.
Table 98, page
in
value in
Table
MCP
and T
and revised T
Table
and removed T
67.
www.xilinx.com
and revised F
and
Table
symbol in
and
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
through
through
Table
26,
RDCK_DI_ECC
Table
60.
Table 72, page
Table 70, page
Table
Characteristics:
Table 10, page
Table
Table 99, page
4.
IDELAYRESOLUTION
7.
83.
85.
80. Changed T
Table
Table
83.
CKSR
Table 66, page
3.
28,
CKSR
INDUTY
Table
Revision
90.
97.
encode only in
Guidelines: Revised values in
in
Guidelines:
Table 65, page
Guidelines:
Guidelines: Revised values in
53.
, F
Table 64, page
51.
(Table
8.
84.
29,
Table
INMAX
OUT_OFFSET
Table
25.
(Table
in
(Table
(Table
46.
62.
56).
,and F
Table 64, page 44
31.
30,
Table
56).
56).
56).
44.
VCOMAX
44.
Table
(Table
in
68.
Table
48,
in
56).
Table
Table 54
Table 74, page
Table 54
80.
Table 92
and added Notes 1 and 2.
Table 85
32,
Table
37.
on
on
Table
through
69.
page
page
through
33,
55.
30.
30.
Table
Table
34,
97.
88