XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 56
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Table 75: PLL in PMCD Mode Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
T
T
CLKIN_FREQ_MAX
CLKIN_FREQ_MIN
CLKIN_DUTY_CYCLE
RES_REL_PULSE_MIN
PLLCCK_REL
PLLCCKO
Symbol
/T
PLLCKC_REL
REL Setup and Hold for all Outputs
Maximum Clock Propagation Delay
Maximum Input Frequency
Minimum Input Frequency
Allowable Input Duty Cycle: 1—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Pulse Width for RST and REL
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
0.00
0.60
710
4.6
-3
1
5
Speed Grade
25/75
30/70
35/65
40/60
45/55
0.00
0.60
710
4.6
-2
1
5
0.00
0.60
645
5.2
-1
1
5
Units
MHz
MHz
ns
ns
ns
%
%
%
%
%
56