XC3SD1800A-5FGG676C Xilinx Inc, XC3SD1800A-5FGG676C Datasheet - Page 41
![SPARTAN-3ADSP FPGA 1800K 676FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3SD1800A-5FGG676C
Manufacturer Part Number
XC3SD1800A-5FGG676C
Description
SPARTAN-3ADSP FPGA 1800K 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-5FGG676C
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Total Ram Bits
1548288
Number Of I /o
519
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-5FGG676C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC3SD1800A-5FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC3SD1800A-5FGG676C
Manufacturer:
XILINX
Quantity:
160
Part Number:
XC3SD1800A-5FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Block RAM Timing
Table 33: Block RAM Timing
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
Clock-to-Output Times
T
T
Setup Times
T
T
T
T
T
T
Hold Times
T
T
T
T
T
T
Clock Timing
T
T
Clock Frequency
F
RCKO_DOA_NC
RCKO_DOA
RCCK_ADDR
RDCK_DIB
RCCK_ENB
RCCK_WEB
RCCK_REGCE
RCCK_RST
RCKC_ADDR
RCKC_DIB
RCKC_ENB
RCKC_WEB
RCKC_REGCE
RCKC_RST
BPWH
BPWL
BRAM
Symbol
The numbers in this table are based on the operating conditions set forth in
When reading from block RAM, the delay from the active transition at
the CLK input to data appearing at the DOUT output
Clock CLK to DOUT output (with output register)
Setup time for the ADDR inputs before the active transition at the CLK
input of the block RAM
Setup time for data at the DIN inputs before the active transition at the
CLK input of the block RAM
Setup time for the EN input before the active transition at the CLK input
of the block RAM
Setup time for the WE input before the active transition at the CLK input
of the block RAM
Setup time for the CE input before the active transition at the CLK input
of the block RAM
Setup time for the RST input before the active transition at the CLK
input of the block RAM
Hold time on the ADDR inputs after the active transition at the CLK
input
Hold time on the DIN inputs after the active transition at the CLK input
Hold time on the EN input after the active transition at the CLK input
Hold time on the WE input after the active transition at the CLK input
Hold time on the CE input after the active transition at the CLK input
Hold time on the RST input after the active transition at the CLK input
High pulse width of the CLK signal
Low pulse width of the CLK signal
Block RAM clock frequency
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Table
7.
0.40
0.29
0.51
0.64
0.34
0.22
0.09
0.09
0.09
0.09
0.09
0.09
1.56
1.56
Min
–
–
0
-5
Speed Grade
Max
2.38
1.24
320
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.46
0.33
0.60
0.75
0.40
0.25
0.10
0.10
0.10
0.10
0.10
0.10
1.79
1.79
Min
–
–
0
-4
Max
2.80
1.45
280
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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