XA3S700A-4FGG400I Xilinx Inc, XA3S700A-4FGG400I Datasheet - Page 12

• Manufacturer Part Number: XA3S700A-4FGG400I
• Description: IC FPGA SPARTAN-3A 700K 400-FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A XAr

Specifications of XA3S700A-4FGG400I

• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards
12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
IOSTANDARD
Attribute
(3)
(3)
(3)
(3)
(3)
(3)
24
16
24
12
16
12
8
4
6
12
16
24
12
16
12
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
2
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(mA)
24
24
Conditions
I
12
16
12
16
24
12
16
12
16
12
OL
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
(7)
(7)
Test
–16
–24
–16
–24
–12
(mA)
–6
–12
–16
–24
–12
–12
–16
–12
I
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–6
–8
–2
–4
–8
–2
–4
–6
–8
–2
–4
–6
OH
(7)
(7)
(7)
(7)
(7)
(7)
Max (V)
V
Characteristics
0.4
0.4
0.4
0.4
0.4
0.4
OL
Logic Level
V
V
V
V
V
CCO
CCO
CCO
CCO
CCO
Min (V)
V
2.4
OH
–
–
–
–
–
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0.4
0.4
0.4
0.4
0.4
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards (Continued)
Notes:
1.
2.
3.
4.
5.
6.
7.
PCI33_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
IOSTANDARD
The numbers in this table are based on the conditions set forth in
Table 8
Descriptions of the symbols used in this table are as follows:
I
I
V
V
V
V
V
V
V
For the LVCMOS and LVTTL standards: the same V
limits apply for both the Fast and Slow slew attributes.
These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see
http://www.xilinx.com/products/design_resources/conn_central/
protocols/pci_pcix.htm. The PCI IOSTANDARD is not supported
on input-only pins. The PCIX IOSTANDARD is available and has
equivalent characteristics, but no PCI-X IP is supported.
DE-RATE by 5% for T
DE-RATE by 20% for T
OL
OH
OL
OH
IL
IH
CCO
REF
TT
Attribute
–
–
–
–
(4)
–
–
–
(5)
(4)
–
(4)
the output current condition under which V
the input voltage that indicates a Low logic level
–
the input voltage that indicates a High logic level
the output current condition under which V
the voltage applied to a resistor termination
the output voltage that indicates a Low logic level
the output voltage that indicates a High logic level
(4)
the reference voltage for setting the input switching threshold
and
the supply voltage for output drivers
(4)
Table
11.
(mA)
24
24
13.4
16.2
Conditions
I
1.5
6.7
8.1
16
16
J
OL
8
8
8
J
(6)
(6)
above 100
above 100
Test
–16
–13.4 V
–16.2
(mA)
–0.5
–6.7
–8.1
–16
I
–8
–8
–8
–8
–8
OH
DS681 (v1.1) February 3, 2009
(6)
o
C
o
V
C
10% V
V
V
V
V
TT
TT
Max (V)
TT
TT
TT
TT
Product Specification
V
– 0.475 V
– 0.475 V
0.4
0.4
0.4
0.4
0.4
Characteristics
– 0.61
– 0.80
OL
– 0.6
– 0.8
Logic Level
CCO
OL
OH
is tested
is tested
V
90% V
V
V
V
V
V
V
OL
V
V
TT
TT
CCO
CCO
CCO
CCO
CCO
TT
TT
Min (V)
TT
TT
and V
V
+ 0.475
+ 0.475
+ 0.61
+ 0.80
OH
+ 0.6
+ 0.8
- 0.4
- 0.4
- 0.4
- 0.4
- 0.4
CCO
OH
R