XA3S500E-4FTG256Q Xilinx Inc, XA3S500E-4FTG256Q Datasheet - Page 27

• Manufacturer Part Number: XA3S500E-4FTG256Q
• Description: IC FPGA SPARTAN-3E 500K 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4FTG256Q

• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 29: Switching Characteristics for the DFS
Notes:
1.
2.
3.
4.
5.
6.
Phase Shifter
Table 30: Recommended Operating Conditions for the PS in Variable Phase Mode
DS635 (v2.0) September 9, 2009
Product Specification
Output Frequency Ranges
CLKOUT_FREQ_FX
Output Clock Jitter
CLKOUT_PER_JITT_FX
Duty Cycle
CLKOUT_DUTY_CYCLE_FX
Phase Alignment
CLKOUT_PHASE_FX
CLKOUT_PHASE_FX180
Lock Time
LOCK_FX
Operating Frequency Ranges
PSCLK_FREQ
(F
Input Pulse Requirements
PSCLK_PULSE
PSCLK
The numbers in this table are based on the operating conditions set forth in
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching). Output
jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching
frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter. Use the
Clocking Wizard to determine jitter for a specific design.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter
of “±[1% of CLKFX period + 300]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 300 ps] = ±400 ps.
Symbol
)
(2)
(5,6)
Symbol
R
(6)
(2,3)
Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
Frequency for the CLKFX and CLKFX180 outputs
Period jitter at the CLKFX and CLKFX180
outputs
Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
Phase offset between the DFS CLKFX output and the DLL CLK0
output when both the DFS and DLL are used
Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts LOCKED
when the CLKFX and CLKFX180 signals
are valid. If using both the DLL and the DFS,
use the longer locking time.
Description
Description
www.xilinx.com
Table 6
5 MHz < F
CLKIN > 20 MHz
F
CLKIN <20 MHz
CLKIN
and
15 MHz
> 15 MHz
Table
CLKIN
28.
<
Device
All
All
All
All
All
All
-4 Speed Grade
40%
Min
1
±[1% of
CLKFX
+ 100]
period
-4 Speed Grade
Min
Typ
5
-
-
-
-
-
See Note 4
Max
60%
167
±[1% of
±[1% of
±[1% of
CLKFX
CLKFX
CLKFX
period
+ 200]
period
+ 400]
period
+ 300]
±200
Max
Max
311
450
5
Units
MHz
Units
MHz
ms
-
ps
ps
ps
ps
ps
μs
27