XA3S500E-4FTG256Q Xilinx Inc, XA3S500E-4FTG256Q Datasheet - Page 20

• Manufacturer Part Number: XA3S500E-4FTG256Q
• Description: IC FPGA SPARTAN-3E 500K 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S500E-4FTG256Q

• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Configurable Logic Block Timing
Table 20: CLB (SLICEM) Timing
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
Propagation Times
T
Set/Reset Pulse Width
T
AS
AH
CKO
DICK
CKDI
CH
CL
TOG
ILO
RPW_CLB
The numbers in this table are based on the operating conditions set forth in
Symbol
R
When reading from the FFX (FFY) Flip-Flop, the time from the active
transition at the CLK input to data appearing at the XQ (YQ) output
Time from the setup of data at the F or G input to the active transition
at the CLK input of the CLB
Time from the setup of data at the BX or BY input to the active
transition at the CLK input of the CLB
Time from the active transition at the CLK input to the point where
data is last held at the F or G input
Time from the active transition at the CLK input to the point where
data is last held at the BX or BY input
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
The time it takes for data to travel from the CLB’s F (G) input to the X
(Y) output
The minimum allowable pulse width, High or Low, to the CLB’s SR
input
Description
www.xilinx.com
Table
6.
-4 Speed Grade
0.52
1.81
0.80
0.80
1.80
Min
0
0
0
-
-
Max
0.60
0.76
572
-
-
-
-
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
20