XC2S150E-6FT256I Xilinx Inc, XC2S150E-6FT256I Datasheet - Page 39

SPARTAN FPGA 150000 GATE 1.8V

XC2S150E-6FT256I

Manufacturer Part Number
XC2S150E-6FT256I
Description
SPARTAN FPGA 150000 GATE 1.8V
Manufacturer
Xilinx Inc
Series
Spartan™-IIEr
Datasheet

Specifications of XC2S150E-6FT256I

Number Of Logic Elements/cells
3888
Number Of Labs/clbs
864
Total Ram Bits
49152
Number Of I /o
182
Number Of Gates
150000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Q1280323

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2S150E-6FT256I
Manufacturer:
XILINX
0
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in
Notes:
1.
DS077-3 (v2.3) June 18, 2008
Product Specification
Propagation Delays
3-state Delays
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Set/Reset Delays
T
T
T
T
IOOCECK
IOSRCKO
IOSRCKT
IOTCECK
T
T
Three-state turn-off delays should not be adjusted.
IOOCK
IOTCK
T
T
T
T
T
T
T
Symbol
T
T
T
T
T
IOTLPON
IOTLPHZ
T
IOGSRQ
IOCKON
IOSRON
IOCKHZ
IOSRHZ
T
IOOLP
IOTON
IOCKP
IOSRP
IOTHZ
IOOP
GTS
/ T
/ T
/ T
/ T
/ T
/ T
R
IOCKOSR
IOCKT
IOCKTCE
IOCKTSR
IOCKO
IOCKOCE
O input to pad
O input to pad via transparent latch
T input to pad high impedance
T input to valid data on pad
T input to pad high impedance via transparent latch
T input to valid data on pad via transparent latch
GTS to pad high impedance
Clock CLK to pad
Clock CLK to pad high impedance (synchronous)
Clock CLK to valid data on pad (synchronous)
O input
OCE input
SR input (OFF)
3-state setup times, T input
3-state setup times, TCE input
3-state setup times, SR input (TFF)
SR input to pad (asynchronous)
SR input to pad high impedance (asynchronous)
SR input to valid data on pad (asynchronous)
GSR to pad
IOB Output Delay Adjustments for Different Standards(1), page
Description
(1)
www.xilinx.com
(1)
Spartan-IIE FPGA Family: DC and Switching Characteristics
(1)
(1)
(1)
1.0 / 0
0.7 / 0
0.9 / 0
0.6 / 0
0.6 / 0
0.9 / 0
Min
1.0
1.2
0.7
1.1
0.8
1.2
1.9
0.9
0.7
1.1
1.2
1.0
1.4
3.8
-7
Speed Grade
Max
2.7
3.1
1.7
2.9
2.0
3.2
4.6
2.8
2.0
3.2
3.3
2.4
3.7
8.5
-
-
-
-
-
-
1.1 / 0
0.7 / 0
1.0 / 0
0.7 / 0
0.8 / 0
1.0 / 0
Min
1.0
1.2
0.7
1.1
0.8
1.2
1.9
0.9
0.7
1.1
1.2
1.0
1.4
3.8
40.
-6
Max
2.9
3.4
1.9
3.1
2.2
3.4
4.9
2.9
2.2
3.4
3.5
2.7
3.9
9.7
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
39

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