EP2S180F1020C4 Altera, EP2S180F1020C4 Datasheet - Page 159

• Manufacturer Part Number: EP2S180F1020C4
• Description: IC STRATIX II FPGA 180K 1020FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S180F1020C4

• Number Of Logic Elements/cells: 179400
• Number Of Labs/clbs: 8970
• Total Ram Bits: 9383040
• Number Of I /o: 742
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 179400
• # I/os (max): 742
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 179400
• Ram Bits: 9383040
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• For Use With: 544-1701 - DSP PRO KIT W/SII EP2S180N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1415

Altera Corporation
April 2011
4.
5.
The Quartus II software reports the timing with the conditions shown in
Table 5–34
circuit that is represented by the output timing of the Quartus II software.
Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to
(1)
(2)
(3)
Figures 5–5
output enable timing.
Record the time to V
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
V
V
CCPD
CCINT
Output
Buffer
Figure
V
GND
CCIO
is 3.085 V unless otherwise specified.
is 1.12 V unless otherwise specified.
using the above equation.
and
5–4:
Output
5–6
V
show the measurement setup for output disable and
MEAS
MEAS
R
.
S
GND
V
TT
R
C
Stratix II Device Handbook, Volume 1
Figure 5–4
T
L
DC & Switching Characteristics
shows the model of the
Output
Output
p
n
R
D
5–23