EP2S180F1020C4 Altera, EP2S180F1020C4 Datasheet - Page 107

• Manufacturer Part Number: EP2S180F1020C4
• Description: IC STRATIX II FPGA 180K 1020FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S180F1020C4

• Number Of Logic Elements/cells: 179400
• Number Of Labs/clbs: 8970
• Total Ram Bits: 9383040
• Number Of I /o: 742
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 179400
• # I/os (max): 742
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 179400
• Ram Bits: 9383040
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• For Use With: 544-1701 - DSP PRO KIT W/SII EP2S180N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1415

Altera Corporation
May 2007
Notes to
(1)
(2)
(3)
(4)
780-pin
FineLine BGA
1,020-pin
FineLine BGA
1,508-pin
FineLine BGA
1,020-pin
FineLine BGA
1,508-pin
FineLine BGA
Table 2–25. EP2S130 Differential Channels
Table 2–26. EP2S180 Differential Channels
Package
Package
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
This is the maximum number of channels the PLLs can directly drive.
This is the maximum number of channels if the device uses cross bank channels from the adjacent center PLL.
The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10.
Tables 2–21
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter/
Transmitter/
Receiver
Receiver
to 2–26:
Channels
Channels
156
156
156
156
64
68
88
92
88
92
Total
Total
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
PLL 1
PLL 1
16
32
17
34
22
44
23
46
37
78
37
78
22
44
23
46
37
78
37
78
Note (1)
Note (1)
Center Fast PLLs
Center Fast PLLs
PLL 2
PLL 2
16
32
17
34
22
44
23
46
41
78
41
78
22
44
23
46
41
78
41
78
PLL 3
PLL 3
16
32
17
34
22
44
23
46
41
78
41
78
22
44
23
46
41
78
41
78
PLL 4
PLL 4
16
32
17
34
22
44
23
46
37
78
37
78
22
44
23
46
37
78
37
78
Stratix II Device Handbook, Volume 1
PLL 7
PLL 7
22
23
37
37
22
23
37
37
-
-
-
-
-
-
-
-
-
-
-
-
Corner Fast PLLs
Corner Fast PLLs
PLL 8
PLL 8
Stratix II Architecture
22
23
41
41
22
23
41
41
-
-
-
-
-
-
-
-
-
-
-
-
PLL 9 PLL 10
PLL 9 PLL 10
22
23
41
41
22
23
41
41
-
-
-
-
-
-
-
-
-
-
-
-
(4)
(4)
22
23
37
37
22
23
37
37
2–99
-
-
-
-
-
-
-
-
-
-