EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 38

IC STRATIX IV GX 290K 1517FBGA

EP4SGX290KF40C3N

Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624

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2–2
Figure 2–1. Stratix IV LAB Structure and Interconnects
Stratix IV Device Handbook Volume 1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
R20
R4
Figure 2–1
The LAB of the Stratix IV device has a derivative called memory LAB (MLAB), which
adds look-up table (LUT)-based SRAM capability to the LAB, as shown in
The MLAB supports a maximum of 640 bits of simple dual-port static random access
memory (SRAM). You can configure each ALM in an MLAB as either a 64 × 1 or a
32 × 2 block, resulting in a configuration of either a 64 × 10 or a 32 × 20 simple
dual-port SRAM block. MLAB and LAB blocks always coexist as pairs in all Stratix IV
families. MLAB is a superset of the LAB and includes all LAB features.
Local Interconnect
shows the Stratix IV LAB structure and interconnects.
LAB
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
C4
from Either Side by Columns & LABs,
C12
Local Interconnect is Driven
& from Above by Rows
Row Interconnects of
Variable Speed & Length
MLAB
ALMs
Column Interconnects of
Variable Speed & Length
February 2011 Altera Corporation
Logic Array Blocks
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Figure
2–2.

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