EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 30

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 9 of 9)
April 2011 Altera Corporation
Digital reset pulse width
Notes to
(1) The
(2) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase jitter
(3) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency
(5) The device cannot tolerate prolonged operation at this absolute maximum.
(6) You must use the 1.1-V RX V
(7) The rate matcher supports only up to
(8) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to
(9) Time for which the CDR must be kept in lock-to-reference (LTR) mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual
(10) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to
(11) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to
(12) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the "Left/Right PLL Requirements
(13) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(14) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the link. You can
(15) Pending Characterization.
(16) The Quartus II software automatically selects the appropriate /L divider depending on the configured data.
(17) The maximum transceiver-FPGA fabric interface speed of 265.625 MHz is allowed only in Basic low-latency PCS mode with a 32-bit interface width. For more
(18)
(19) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels physically
(20) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the
(21) The rise and fall time transition is specified from 20% to 80%.
(22) Stratix IV GX devices in -4 speed grade support Basic mode and deterministic latency mode transceiver configurations up to 6375 Mbps. These configurations
EP4SGX230DF29, EP4SGX110FF35, EP4SGX180DF29, EP4SGX230FF35, EP4SGX290FF35, EP4SGX180FF35, EP4SGX290FH29, EP4SGX360FF35, and
EPSGX360FH29.
at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more information, refer to the
Reconfiguration in Stratix IV Devices
mode. Refer to
in Basic (PMA Direct) Mode" section in the
bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about clocking requirements in this
mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the
information, refer to the “Basic Double-Width Mode Configurations” section in the
Figure 1–1
located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two
of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to derive the minimum eye opening
requirement with Receiver Equalization enabled.
are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the
Description
Symbol/
–
Table
2× speed grade is the fastest speed grade offered in the following Stratix IV GX devices: EP4SGX70DF29, EP4SGX110DF29, EP4SGX110FF35,
1–23:
shows the AC gain curves for each of the 16 available equalization settings.
Figure 1–2 on page
ICM
Conditions
setting if the input serial data standard is LVDS.
—
1–31.
chapter.
±
300 parts per million (ppm).
Transceiver Clocking in Stratix IV Devices
Min
–2 Commercial
Speed Grade
Typ
Transceiver Architecture in Stratix IV Devices
Transceiver Clocking in Stratix IV Devices
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Max
Minimum is two parallel clock cycles
Transceiver Architecture in Stratix IV Devices
Min
Commercial/Industrial
chapter.
Speed Grade
Figure 1–2 on page
–2× Commercial
Typ
and
–3
Figure 1–2 on page
Figure 1–3 on page
(1)
Max
1–31.
chapter.
chapter.
Commercial/Industrial
Min
1–31.
Speed Grade
1–31.
Typ
chapter.
–4
1–22
Max
Dynamic
Unit
—