EP2SGX130GF1508I4N Altera, EP2SGX130GF1508I4N Datasheet - Page 33

• Manufacturer Part Number: EP2SGX130GF1508I4N
• Description: IC STRATIX II GX 130K 1508-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX130GF1508I4N

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 734
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1508-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 734
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1508
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2175

Altera Corporation
October 2007
Rate Matcher
Rate matcher is available in Basic, PCI Express, XAUI, and GIGE modes
and consists of a 20-word deep FIFO buffer and a FIFO controller.
Figure 2–20
Stratix II GX device.
Figure 2–20. Rate Matcher
In a multi-crystal environment, the rate matcher compensates for up to a
± 300-PPM difference between the source and receiver clocks.
shows the standards supported and the PPM for the rate matcher
tolerance.
Basic Mode
In Basic mode, you can program the skip and control pattern for rate
matching. In single-width Basic mode, there is no restriction on the
deletion of a skip character in a cluster. The rate matcher deletes the skip
characters as long as they are available. For insertion, the rate matcher
inserts skip characters such that the number of skip characters at the
output of rate matcher does not exceed five. In double-width mode, the
rate matcher deletes skip character when they appear as pairs in the
upper and lower bytes. There are no restrictions on the number of skip
characters that are deleted. The rate matcher inserts skip characters as
pairs.
Note to
(1)
XAUI
PCI Express (PIPE)
GIGE
Basic Double-Width
Table 2–8. Rate Matcher PPM Support
Refer to the
Table
shows the implementation of the rate matcher in the
2–8:
Standard
Stratix II GX Transceiver User Guide
datain
wrclock
rdclock
Matcher
Stratix II GX Device Handbook, Volume 1
Rate
Note (1)
dataout
for the Altera
Stratix II GX Architecture
± 100
± 300
± 100
± 300
PPM
®
-defined scheme.
Table 2–8
2–25