EP2SGX130GF1508I4N Altera, EP2SGX130GF1508I4N Datasheet - Page 155

• Manufacturer Part Number: EP2SGX130GF1508I4N
• Description: IC STRATIX II GX 130K 1508-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX130GF1508I4N

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 734
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1508-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 734
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1508
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2175

Altera Corporation
October 2007
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02 changes:
June 2006, v1.2
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April 2006, v1.1
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02 changes:
October 2005
v1.0
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03 changes:
August 2006, v1.4
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June 2006, v1.3
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April 2006, v1.2
Table 2–42. Document Revision History (Part 5 of 6)
Document
Date and
Version
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Added chapter to the Stratix II GX Device
Handbook.
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Updated notes 1 and 2 in Figure 2–1.
Updated “Byte Serializer” section.
Updated Tables 2–4, 2–7, and 2–16.
Updated “Programmable Output Driver”
section.
Updated Figure 2–12.
Updated “Programmable Pre-Emphasis”
section.
Added Table 2–11.
Added “Dynamic Reconfiguration” section.
Added “Calibration Block” section.
Updated “Programmable Equalizer”
section, including addition of Figure 2–18.
Updated Figure 2–3.
Updated Figure 2–7.
Updated Table 2–4.
Updated “Transmit Buffer” section.
Updated Table 3–18 with note.
Updated note 2 in Figure 3–41.
Updated column title in Table 3–21.
Updated note 1 in Table 3–9.
Updated note 1 in Figure 3–40.
Updated note 2 in Figure 3–41.
Updated Table 3–16.
Updated Figure 3–56.
Updated Tables 3–19 through 3–22.
Updated Tables 3–25 and 3–26.
Updated “Fast PLL & Channel Layout”
section.
Changes Made
Stratix II GX Device Handbook, Volume 1
Updated input frequency range in
Table 2–4.
Updated input frequency range in
Table 2–4.
Added 1,152-pin FineLine BGA package
information for EP2SGX60 device in
Table 3–16.
Summary of Changes
Stratix II GX Architecture
2–147