EP2S130F1020C5 Altera, EP2S130F1020C5 Datasheet - Page 70

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EP2S130F1020C5

Manufacturer Part Number
EP2S130F1020C5
Description
IC STRATIX II FPGA 130K 1020-FBG
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S130F1020C5

Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1459

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PLLs & Clock Networks
2–62
Stratix II Device Handbook, Volume 1
Figure 2–42. Global & Regional Clock Connections from Corner Clock Pins &
Fast PLL Outputs
Note to
(1)
The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input can be driven by an output from
another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated
global signal cannot drive the PLL.
Figure
2–42:
Note (1)
Altera Corporation
May 2007

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