EP2S90F1020C3 Altera, EP2S90F1020C3 Datasheet - Page 80
EP2S90F1020C3
Manufacturer Part Number
EP2S90F1020C3
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1020C3
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1917
EP2S90F1020C3
EP2S90F1020C3
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I/O Structure
Figure 2–47. Row I/O Block Connection to the Interconnect
Note to
(1)
2–72
Stratix II Device Handbook, Volume 1
Interconnect
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
LAB Local
Figure
Interconnects
to Adjacent LAB
R4 & R24
Interconnect
2–47:
Direct Link
LAB
io_dataina[3..0]
io_datainb[3..0]
C4 Interconnect
to Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Note (1)
Interconnect
io_clk[7:0]
32
Horizontal
I/O Block
up to Four IOEs
Block Contains
Horizontal I/O
Altera Corporation
32 Data & Control
Signals from
Logic Array (1)
May 2007
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