EP2S90F1020C3 Altera, EP2S90F1020C3 Datasheet - Page 110
EP2S90F1020C3
Manufacturer Part Number
EP2S90F1020C3
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1020C3
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1917
EP2S90F1020C3
EP2S90F1020C3
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High-Speed Differential I/O with DPA Support
Figure 2–60. Fast PLL & Channel Layout in the EP2S15 & EP2S30 Devices
Note to
(1)
2–102
Stratix II Device Handbook, Volume 1
4
See
2
2
Figure
Table 2–21
4
4
2–60:
PLL 1
PLL 2
Fast
Fast
LVDS
LVDS
Clock
Clock
for the number of channels each device supports.
For high-speed source synchronous interfaces such as POS-PHY 4,
Parallel RapidIO, and HyperTransport, the source synchronous clock rate
is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols since the source synchronous clock does not
provide a byte or word boundary since the clock is one half the data rate,
not one eighth. The Stratix II device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for user-
controlled byte boundary shifting. This simplifies designs while saving
ALM resources. You can use an ALM-based state machine to signal the
shift of receiver byte boundaries until a specified pattern is detected to
indicate byte alignment.
Fast PLL & Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left and right side of the device has one receiver channel and
one transmitter channel per LAB row.
channel layout in the EP2S15 and EP2S30 devices.
fast PLL and channel layout in the EP2S60 to EP2S180 devices.
Clock
Clock
DPA
DPA
Quadrant
Quadrant
Quadrant
Quadrant
Figure 2–60
Clock
Clock
DPA
DPA
Note (1)
shows the fast PLL and
Figure 2–61
LVDS
LVDS
Clock
Clock
Altera Corporation
PLL 4
PLL 3
Fast
Fast
4
4
shows the
May 2007
2
2
4
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