EP1S60F1020C5N Altera, EP1S60F1020C5N Datasheet - Page 19
EP1S60F1020C5N
Manufacturer Part Number
EP1S60F1020C5N
Description
IC STRATIX FPGA 60K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S60F1020C5N
Number Of Logic Elements/cells
57120
Number Of Labs/clbs
5712
Total Ram Bits
5215104
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
EP1S60F1020C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
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Manufacturer:
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Quantity:
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Figure 2–3. Direct Link Connection
Altera Corporation
July 2005
block, DSP block, or IOE output
Direct link interconnect from
left LAB, TriMatrix memory
interconnect
Direct link
to left
Interconnect
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include two clocks, two clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load,
synchronous load, and add/subtract control signals. This gives a
maximum of 10 control signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can
also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal will also use labclkena1. If
the LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal will turn off
the LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
Local
LAB
Stratix Device Handbook, Volume 1
Direct link
interconnect
to right
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
Stratix Architecture
2–5
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