EP1SGX40GF1020C5 Altera, EP1SGX40GF1020C5 Datasheet - Page 128

• Manufacturer Part Number: EP1SGX40GF1020C5
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Digital Signal Processing Block
Figure 4–36. Multiply-Accumulate Mode
Notes to
(1)
(2)
4–62
Stratix GX Device Handbook, Volume 1
These signals are not registered or registered once to match the data path pipeline.
These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Data B
Data A
Figure
Shiftout B Shiftout A
4–36:
Shiftin B
ENA
ENA
D
D
CLRN
CLRN
Shiftin A
Q
Q
Multiply-Accumulator Mode
In multiply-accumulator mode (see
multiplied results to the adder/subtractor/accumulator block configured
as an accumulator. You can implement one or two multiply-accumulators
up to 18
blocks are unused in this mode, since only one multiplier can feed one of
two accumulators. The multiply-accumulator output can be up to 52
bits—a maximum of a 36-bit result with 16 bits of accumulation. The
accum_sload and overflow signals are only available in this mode.
The addnsub signal can set the accumulator for decimation and the
overflow signal indicates underflow condition.
Two-Multipliers Adder Mode
The two-multipliers adder mode uses the adder/subtractor/accumulator
block to add or subtract the outputs of the multiplier block, which is
useful for applications such as FFT functions and complex FIR filters. A
single DSP block can implement two sums or differences from two
18
multipliers each.
signa (1)
signb (1)
clock
×
ena
aclr
18-bit multipliers each or four sums or differences from two 9
×
18 bits in one DSP block. The first and third multiplier sub-
ENA
D
CLRN
Q
accum_sload (2)
addnsub (2)
signa (2)
signb (2)
Figure
Accumulator
4–36), the DSP block drives
ENA
D
CLRN
Q
Altera Corporation
February 2005
Data Out
overflow
×
9-bit