EP1SGX40GF1020C5 Altera, EP1SGX40GF1020C5 Datasheet - Page 112

• Manufacturer Part Number: EP1SGX40GF1020C5
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Digital Signal Processing Block
Figure 4–27. Single-Port Mode
Digital Signal
Processing
Block
4–46
Stratix GX Device Handbook, Volume 1
address[ ]
outclken
outclock
inclken
inclock
data[ ]
wren
8 LAB Row
Clocks
8
The most commonly used DSP functions are finite impulse response (FIR)
filters, complex FIR filters, infinite impulse response (IIR) filters, fast
Fourier transform (FFT) functions, direct cosine transform (DCT)
functions, and correlators. All of these blocks have the same fundamental
building block: the multiplier. Additionally, some applications need
specialized operations such as multiply-add and multiply-accumulate
operations. Stratix GX devices provide DSP blocks to meet the arithmetic
requirements of these functions.
Each Stratix GX device has two columns of DSP blocks to efficiently
implement DSP functions faster than LE-based implementations. Larger
Stratix GX devices have more DSP blocks per column (see
Each DSP block can be configured to support up to:
■
■
■
As indicated, the Stratix GX DSP block can support one 36 × 36-bit
multiplier in a single DSP block. This is true for any matched sign
multiplications (either unsigned by unsigned or signed by signed), but
Eight 9 × 9-bit multipliers
Four 18 × 18-bit multipliers
One 36 × 36-bit multiplier
D
ENA
D
ENA
Q
Q
Generator
D
ENA
Pulse
Write
Q
Data In
Address
Write Enable
RAM/ROM
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
256 × 16
512 × 8
D
ENA
Q
Altera Corporation
Table
February 2005
To MultiTrack
Interconnect
4–12).