EP2S60F1020C3 Altera, EP2S60F1020C3 Datasheet - Page 209

• Manufacturer Part Number: EP2S60F1020C3
• Description: IC STRATIX II FPGA 60K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F1020C3

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 718
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 718
• Frequency (max): 816.99MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1130; EP2S60F1020C3ES

Altera Corporation
April 2011
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
1.2-V Differential
HSTL
3.3-V LVTTL
3.3-V LVCMOS
2.5-V
LVTTL/LVCMOS
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 5 of 5)
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 1 of 5)
I/O Standard
I/O Standard
The toggle rate applies to 0-pF output load for all I/O standards except for LVDS and HyperTransport technology
on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from
0 to 5pF.
1.2-V HSTL is only supported on column I/O pins in I/O banks 4, 7, and 8.
Differential HSTL and SSTL is only supported on column clock and DQS outputs.
HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
LVPECL is only supported on column clock pins.
Refer to
for PLL output.
Table
Tables 5–81
5–78:
Strength
OCT 50 Ω
12 mA
16 mA
20 mA
24 mA
12 mA
16 mA
20 mA
24 mA
12 mA
16 mA
Strength
Drive
4 mA
8 mA
4 mA
8 mA
4 mA
8 mA
Drive
through
5–91
478
260
213
136
138
134
377
206
141
108
387
163
142
120
83
65
-3
Column I/O Pins (MHz)
280
-3
Column I/O Pins
if using SERDES block. Use the toggle rate values from the clock output column
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
510
333
247
197
187
177
391
212
145
111
427
224
203
182
88
72
-4
-4
-
510
333
247
197
187
177
391
212
145
111
427
224
203
182
88
72
-5
-5
-
478
260
213
377
206
387
163
142
-3
-
-
-
-
-
-
-
-
Row I/O Pins (MHz)
Row I/O Pins
-3
-
510
333
247
391
212
427
224
203
-4
-
-
-
-
-
-
-
-
Stratix II Device Handbook, Volume 1
-4
-
DC & Switching Characteristics
510
333
247
391
212
427
224
203
-5
-
-
-
-
-
-
-
-
-5
-
Note (1)
Dedicated Clock Outputs
466
291
211
166
154
143
377
178
115
391
170
152
134
86
79
74
-3
Clock Outputs (MHz)
280
-3
510
333
247
197
187
177
391
212
145
111
427
224
203
182
88
72
-4
-4
-
510
333
247
197
187
177
391
212
145
111
427
224
203
182
88
72
-5
-5
5–73
-