EP2S60F1020C3 Altera, EP2S60F1020C3 Datasheet - Page 153

• Manufacturer Part Number: EP2S60F1020C3
• Description: IC STRATIX II FPGA 60K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F1020C3

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 718
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 718
• Frequency (max): 816.99MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1130; EP2S60F1020C3ES

Altera Corporation
April 2011
Low
sustaining
current
High
sustaining
current
Low
overdrive
current
High
overdrive
current
Bus-hold
trip point
25-Ω R
3.3/2.5
Parameter Conditions
Table 5–29. Bus Hold Parameters
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2)
Notes (1)
Symbol
S
,
2
Internal series termination with
calibration (25-Ω setting)
Internal series termination without
calibration (25-Ω setting)
V
(maximum)
V
(minimum)
0 V < V
V
0 V < V
V
IN
IN
CCIO
CCIO
> V
< V
IL
IH
IN
IN
<
<
Description
–22.5
22.5
0.45
Min
Bus Hold Specifications
Table 5–29
On-Chip Termination Specifications
Tables 5–30
resistance tolerance when using series or differential on-chip termination.
1.2 V
–120
Max
0.95
120
shows the Stratix II device family bus hold specifications.
and
–25.0
25.0
0.50
Min
1.5 V
V
V
5–31
C C I O
C C I O
–160
Max
1.00
160
Conditions
define the specification for internal termination
= 3.3/2.5 V
= 3.3/2.5 V
–30.0
V
30.0
0.68
Min
CCIO
1.8 V
Level
–200
Max
1.07
200
Stratix II Device Handbook, Volume 1
Commercial
–50.0
50.0
0.70
Min
Max
±30
±5
DC & Switching Characteristics
2.5 V
Resistance Tolerance
–300
Max
1.70
300
Industrial
–70.0
70.0
0.80
Min
Max
±10
±30
3.3 V
–500
Max
2.00
500
Unit
%
%
Unit
5–17
μA
μA
μA
μA
V