EP1SGX25DF672C5N Altera, EP1SGX25DF672C5N Datasheet - Page 253

• Manufacturer Part Number: EP1SGX25DF672C5N
• Description: IC STRATIX GX FPGA 25K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF672C5N

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Decrease input delay to
internal cells
Decrease input delay to
input register
Decrease input delay to
output register
Increase delay to output
pin
Increase delay to output
enable pin
Increase output clock
enable delay
Increase input clock enable
delay
Increase output enable
clock enable delay
Table 6–78. Stratix GX IOE Programmable Delays on Column Pins
Parameter
Off
On
Small
Medium
Large
Off
On
Off
On
Off
On
Off
On
Off
On
Small
Large
Off
On
Small
Large
Off
On
Small
Large
Tables 6–78
programmable delays, respectively. These delays are controlled with the
Quartus II software logic options listed in the Parameter column.
Setting
-5 Speed Grade
and
Min
6–79
3,970
3,390
2,810
1,240
1,016
1,016
1,016
1,016
1,016
1,016
3900
show the adder delays for the column and row IOE
Max
212
212
377
338
540
540
540
0
0
0
0
0
0
0
-6 Speed Grade
Min
Stratix GX Device Handbook, Volume 1
4,367
3,729
3,091
4,290
1,364
1,118
1,118
1,118
1,118
1,118
1,118
Max
224
224
397
372
594
594
594
0
0
0
0
0
0
0
DC & Switching Characteristics
-7 Speed Grade
Min
5,022
4,288
3,554
4,933
1,568
1,285
1,285
1,285
1,285
1,285
1,285
Max
257
257
456
427
683
683
683
0
0
0
0
0
0
0
Unit
6–51
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps