EP20K400EFC672-2X Altera, EP20K400EFC672-2X Datasheet - Page 25

IC APEX 20KE FPGA 400K 672-FBGA

EP20K400EFC672-2X

Manufacturer Part Number
EP20K400EFC672-2X
Description
IC APEX 20KE FPGA 400K 672-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K400EFC672-2X

Number Of Logic Elements/cells
16640
Number Of Labs/clbs
1664
Total Ram Bits
212992
Number Of I /o
488
Number Of Gates
1052000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
APEX 20K
Number Of Usable Gates
400000
Number Of Logic Blocks/elements
16640
# Registers
104
# I/os (max)
488
Frequency (max)
223MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
16640
Ram Bits
212992
Device System Gates
1052000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2095

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Altera Corporation
Note to
(1)
Row I/O Pin
Column I/O
Pin
LE
ESB
Local
Interconnect
MegaLAB
Interconnect
Row
FastTrack
Interconnect
Column
FastTrack
Interconnect
FastRow
Interconnect
Table 9. APEX 20K Routing Scheme
Source
This connection is supported in APEX 20KE devices only.
Table
9:
I/O Pin
Row
v
Column
I/O Pin
v
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local
interconnect; therefore, it can be driven by the MegaLAB interconnect or
the adjacent LAB. Also, nine ESB macrocells feed back into the ESB
through the local interconnect for higher performance. Dedicated clock
pins, global signals, and additional inputs from the local interconnect
drive the ESB control signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register.
shows the ESB in product-term mode.
v
LE
ESB
v
Interconnect
APEX 20K Programmable Logic Device Family Data Sheet
Local
(1)
v
v
v
v
v
Destination
Interconnect
MegaLAB
v
v
v
v
v
Interconnect
FastTrack
Row
v
v
v
v
Interconnect
FastTrack
Column
v
v
v
v
v
Figure 13
Interconnect
FastRow
(1)
v
25

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