EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 83

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–61. Memory Output Clock Jitter Specification for Arria II GX Devices
Table 1–62. Memory Output Clock Jitter Specification for Arria II GZ Devices
December 2010 Altera Corporation
Duty cycle jitter
Notes to
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
(3) The memory output clock jitter stated in
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a
(3) The memory output clock jitter stated in
clock network.
PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
Parameter
Table
Table
Parameter
1–61:
1–62:
Table 1–62
Duty Cycle Distortion (DCD) Specifications
Table 1–63
Table 1–63. Duty Cycle Distortion on I/O Pins for Arria II GX Devices
Output Duty Cycle
Note to
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
Network
Global
Clock
purpose I/O pins.
Table
Regional
Regional
Regional
Symbol
Network
Global
Global
Global
Clock
lists the memory output clock jitter specifications for Arria II GZ devices.
lists the worst-case DCD specifications for Arria II GX devices.
1–63:
Table 1–61
Table 1–62
Symbol
t
JIT(duty)
is applicable when an input jitter of 30 ps is applied.
is applicable when an input jitter of 30 ps is applied.
Symbol
t
t
t
t
t
t
JIT(duty)
JIT(duty)
JIT(per)
JIT(per)
JIT(cc)
JIT(cc)
Min
45
-100
Min
C4
–4
Max
55
Max
100
-82.5
-82.5
-110
-165
Min
-55
-90
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Min
45
–3
I3, C5, I5
-125
Min
82.5
82.5
Max
110
165
55
90
Max
(Note
(Note
55
–5
1), (2),
Max
1), (2),
125
Min
45
-82.5
-82.5
-110
-165
Min
-55
-90
C6
(Note 1)
(3)
(3)
-125
Min
Max
(Part 2 of 2)
55
–4
–6
82.5
82.5
Max
110
165
55
90
Max
125
Unit
%
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
1–75