EP20K400EBI652-2X Altera, EP20K400EBI652-2X Datasheet - Page 73
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EP20K400EBI652-2X
Manufacturer Part Number
EP20K400EBI652-2X
Description
IC APEX 20KE FPGA 400K 652-BGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K400EBI652-2X
Number Of Logic Elements/cells
16640
Number Of Labs/clbs
1664
Total Ram Bits
212992
Number Of I /o
488
Number Of Gates
1052000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
652-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ESBDATACO2
ESBDD
PD
PTERMSU
PTERMCO
F1-4
F5-20
F20+
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
INSU
INH
OUTCO
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
Table 31. APEX 20K f
Table 32. APEX 20K External Timing Parameters
Table 33. APEX 20K External Bidirectional Timing Parameters
Symbol
Symbol
Symbol
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
Hold time for bidirectional pins with global clock at same-row or same-
column LE register
Clock-to-output delay for bidirectional pins with global clock at IOE
register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate = off
MAX
ESB clock-to-output delay without output registers
ESB data-in to data-out delay for RAM mode
ESB macrocell input to non-registered output
ESB macrocell register setup time before clock
ESB macrocell register clock-to-output delay
Fanout delay using local interconnect
Fanout delay using MegaLab Interconnect
Fanout delay using FastTrack Interconnect
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear pulse width
LE preset pulse width
Clock high time
Clock low time
Write pulse width
Read pulse width
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
Timing Parameters
Tables 32
and
33
describe APEX 20K external timing parameters.
APEX 20K Programmable Logic Device Family Data Sheet
(Part 2 of 2)
Parameter
Note (1)
Clock Parameter
Parameter
Note (1)
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
Conditions
73