EP20K400EBI652-2X Altera, EP20K400EBI652-2X Datasheet - Page 40
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EP20K400EBI652-2X
Manufacturer Part Number
EP20K400EBI652-2X
Description
IC APEX 20KE FPGA 400K 652-BGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K400EBI652-2X
Number Of Logic Elements/cells
16640
Number Of Labs/clbs
1664
Total Ram Bits
212992
Number Of I /o
488
Number Of Gates
1052000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
652-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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APEX 20K Programmable Logic Device Family Data Sheet
40
APEX 20KE devices include an enhanced IOE, which drives the FastRow
interconnect. The FastRow interconnect connects a column I/O pin
directly to the LAB local interconnect within two MegaLAB structures.
This feature provides fast setup times for pins that drive high fan-outs
with complex logic, such as PCI designs. For fast bidirectional I/O timing,
LE registers using local routing can improve setup times and OE timing.
The APEX 20KE IOE also includes direct support for open-drain
operation, giving faster clock-to-output for open-drain signals. Some
programmable delays in the APEX 20KE IOE offer multiple levels of delay
to fine-tune setup and hold time requirements. The Quartus II software
compiler can set these delays automatically to minimize setup time while
providing a zero hold time.
Table 11
options in the Quartus II software.
The register in the APEX 20KE IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, an asynchronous preset can control the register.
shows how fast bidirectional I/O pins are implemented in APEX 20KE
devices. This feature is useful for cases where the APEX 20KE device
controls an active-low input or another device; it prevents inadvertent
activation of the input upon power-up.
Input Pin to Core Delay
Input Pin to Input Register Delay
Core to Output Register Delay
Output Register t
Clock Enable Delay
Table 11. APEX 20KE Programmable Delay Chains
Programmable Delays
describes the APEX 20KE programmable delays and their logic
CO
Delay
Decrease input delay to internal cells
Decrease input delay to input registers
Decrease input delay to output register
Increase delay to output pin
Increase clock enable delay
Quartus II Logic Option
Altera Corporation
Figure 26