EP1S30F780C7 Altera, EP1S30F780C7 Datasheet - Page 118
![IC STRATIX FPGA 30K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S30F780C7
Manufacturer Part Number
EP1S30F780C7
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S30F780C7
Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1421
EP1S30SF780C7
EP1S30SF780C7
Available stocks
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Manufacturer
Quantity
Price
Part Number:
EP1S30F780C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S30F780C7N
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ALTERA30
Quantity:
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Part Number:
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I/O Structure
I/O Structure
2–104
Stratix Device Handbook, Volume 1
Control Signals
The fast PLL has the same lock output, pllenable input, and areset
input control signals as the enhanced PLL.
If the input clock stops and causes the PLL to lose lock, then the PLL must
be reset for correct phase shift operation.
For more information on high-speed differential I/O support, see
Speed Differential I/O Support” on page
IOEs provide many features, including:
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The IOE in Stratix devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer.
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Differential on-chip termination for LVDS I/O standard
Programmable pull-up during configuration
Output drive strength control
Slew-rate control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Double-data rate (DDR) Registers
Figure 2–59
shows the Stratix IOE structure. The
2–130.
Altera Corporation
July 2005
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