EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 126

• Manufacturer Part Number: EP1SGX25CF672C7
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C7

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 4.38597GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Digital Signal Processing Block
Figure 4–34. Simple Multiplier Mode
Note to
(1)
4–60
Stratix GX Device Handbook, Volume 1
Data B
Data A
These signals are not registered or registered once to match the data path pipeline.
Figure
shiftout B
4–34:
shiftin B
shiftout A
ENA
ENA
D
D
CLRN
CLRN
DSP blocks can also implement one 36
mode. DSP blocks use four 18
dedicated adder and internal shift circuitry to achieve 36-bit
multiplication. The input shift register feature is not available for the
36
that is normally a multiplier-result-output register as a pipeline stage for
the 36
mode.
shiftin A
signa (1)
signb (1)
×
Q
Q
clock
36-bit multiplier. In 36
ena
aclr
×
36-bit multiplier.
ENA
D
Figure 4–35
CLRN
×
36-bit mode, the device can use the register
Q
×
18-bit multipliers combined with
shows the 36
×
36-bit multiplier in multiplier
ENA
D
CLRN
Q
×
36-bit multiply
Altera Corporation
February 2005
Data Out