EP3C120F780I7 Altera, EP3C120F780I7 Datasheet - Page 144

• Manufacturer Part Number: EP3C120F780I7
• Description: IC CYCLONE III FPGA 120K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780I7

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 531
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

7–20
Table 7–6. Chapter Revision History (Part 2 of 2)
Cyclone III Device Handbook, Volume 1
May 2008
July 2007
March 2007
Date
Version
1.2
1.1
1.0
Changes include addition of BLVD information
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Initial release.
Updated “Introduction” section with BLVDS information.
Updated Figure 7–1 with BLVDS information and added Note 5.
Updated Table 7–1 and added BLVDS information.
Updated “Cyclone III High-Speed I/O Banks” section with BLVDS information.
Updated Table 7–2 and 7–6.
Added new section “BLVDS I/O Standard Support in Cyclone III Devices”.
Updated Note 4 to Figure 7–4.
Updated Note 1 to Figure 7–10.
Updated Note 1 to Figure 7–11.
Updated Note 1 to Figure 7–14.
Updated “Mini-LVDS I/O Standard Support in Cyclone III Devices” section.
Updated Note 1 to Figure 7–17.
Updated “LVPECL I/O Support in Cyclone III Devices” section.
Added new Figure 7–18.
Added note that PLL output clock pins do not support Class II type of
selected differential I/O standards.
Added Table 8–3 that lists the number of differential channels which are
migratable across densities and packages.
Updated (Note 4) to Figure 7–1.
Updated (Note 3) to Table 7–1.
Added new Table 7–3.
Added (Note 1) to Figure 7–21.
Added (Note 1) to Figure 7–23.
Added chapter TOC and “Referenced Documents” section.
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Changes Made
© December 2009 Altera Corporation
Chapter Revision History