EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 37
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 2 of 6)
December 2010 Altera Corporation
fixedclk clock frequency
reconfig_clk clock
frequency
Delta time between
reconfig_clks
Transceiver block minimum
power-down
(gxb_powerdown) pulse
width
Receiver
Supported I/O Standards
Data rate
Absolute V
pin
Operational V
receiver pin
Absolute V
pin
Maximum peak-to-peak
differential input voltage V
(diff p-p) before device
configuration
Maximum peak-to-peak
differential input voltage V
(diff p-p) after device
configuration
Minimum differential eye
opening at receiver serial
input pins
V
Receiver DC Coupling
Support
ICM
(2)
Description
Symbol/
MAX
MIN
(14)
MAX
for a receiver
for a receiver
for a
(13)
ID
ID
V
Data Rate > 5 Gbps
V
ICM
ICM
clock frequency
Equalization = 0
Equalization = 0
reconfiguration
DC gain = 0 dB
DC gain = 0 dB
PCIe Receiver
V
V
600 Mbps to
Conditions
Data Rate =
ICM
ICM
= 1.1 V setting
=1.1 V setting
Dynamic
5 Gbps
setting
setting
Detect
= 0.82 V
= 0.82 V
—
—
—
—
—
—
—
—
(3)
(3)
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
For more information about receiver DC coupling support, refer to the
“DC-Coupled Links” section in the
Devices
37.5
Min
2.5/
-0.4
600
100
165
—
—
—
—
—
—
—
(2)
1
–C3 and –I3
chapter.
1100 ± 10%
820 ± 10%
125
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
(1)
6375
Max
1.6
1.5
1.6
2.7
1.6
—
50
—
—
—
—
2
37.5
Min
2.5/
-0.4
600
165
165
—
—
—
—
—
—
—
Transceiver Architecture for Arria II
(2)
1
–C4 and –I4
1100 ± 10%
820 ± 10%
Typ
125
—
—
—
—
—
—
—
—
—
—
—
—
3750
Max
1.6
1.5
1.6
2.7
1.6
—
50
—
—
—
—
2
Mbps
MHz
MHz
Unit
ms
mV
mV
mV
mV
µs
V
V
V
V
V
V
1–29